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3.2.7
c1, Control Register
ARM DDI 0301H
ID012310
This section contains information on:
•
Purpose of the Control Register
•
Structure of the Control Register
•
Operation of the Control Register on page 3-45
•
Use of the Control Register on page 3-47
•
Behavior of the Control Register on page 3-48.
Purpose of the Control Register
The purpose of the Control Register is to provide control and configuration of:
•
memory alignment, endianness, protection, and fault behavior
•
MMU and cache enables and cache replacement strategy
•
interrupts and the behavior of interrupt latency
•
the location for exception vectors
•
program flow prediction.
Table 3-39 on page 3-45 lists the purposes of the individual bits in the Control Register.
Structure of the Control Register
The Control Register is:
•
in CP15 c1
•
a 32 bit register, Table 3-39 on page 3-45 lists read and write access to individual bits for
the Secure and Non-secure worlds
•
accessible in privileged modes only
•
partially banked, Table 3-39 on page 3-45 lists banked and Secure modify only bits.
Figure 3-26 shows the arrangement of bits in the register.
31
30 29
28
27
26
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
F
T
E
V
SBZ
SBZ
A
R
E
E
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S
X
D
R
U FI SBZ IT
B
L4
P
T
R
Z
System Control Coprocessor
4 3 2 1 0
V I Z F R S B
SBO
Figure 3-26 Control Register format
W C A
M
3-44
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