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B2.26
CPUECTLR_EL1, CPU Extended Control Register, EL1
The CPUECTLR_EL1 provides additional
the core.
Bit field descriptions
CPUECTLR_EL1 is a 64-bit register, and is part of the 64-bit registers functional group.
This register resets to value
63
62 61 60 59
MXP_EN
MXP_TP
MXP_ATHR
31
30 29
ATOMIC_ST_NEAR
ATOMIC_REL_NEAR
ATOMIC_LD_NEAR
TLD_PRED_DIS
DTLB_CABT_EN
WS_THR_L2
WS_THR_L3
WS_THR_L4
WS_THR_DRAM
WS_THR_DCZVA
RES
RES0, [63:62]
MXP_EN, [61]
100798_0300_00_en
0x0000000961563000
58
57
56
55
54
53 52
51
MM_VMID_THR
MM_ASP_EN
MM_CH_DIS
MM_TLBPF_DIS
HPA_MODE
HPA_CAP
HPA_L1_DIS
HPA_DIS
28
27 26
25
24
23
22
21
20
19 18
0
Reserved.
RES0
Max-power throttle enable. The possible values are:
Disables max-power throttling mechanism. This is the reset value.
0
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B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
IMPLEMENTATION DEFINED
.
50
49
48
47 46
45 44
43
42
41
40
L2_FLUSH
17
16
15
14 13 12
11
9
8
PF_SS_L2_DIST
PF_DIS
Figure B2-22 CPUECTLR_EL1 bit assignments
reserved.
Non-Confidential
B2 AArch64 system registers
configuration and control options for
39
38 37
36
35
34
33
32
ATOMIC_ACQ_NEAR
CA_EVICT_DIS
CA_UCLEAN_EVICT_EN
PFT_IF
PFT_LS
PFT_MM
7
6
5
4
3
2
1
0
EXTLLC
RPF_PHIT_EN
RPF_LO_CONF
RPF_DIS
PF_STS_DIS
PF_STI_DIS
B2-172
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