STMicroelectronics SPC572L series Reference Manual page 2053

RM0400
Date
27-Feb-2015
Table 1150. Revision history(Continued)
Rev
Section 1.3.2.6, Data Control Register 1
"Reset value changes depending on the number of channels that are
enabledon..."
Section 1.3.2.15, DMA Slow Serial Message Bit3 Read Register
(DMA_SMSG_BIT3):
– Changed fields "ID[7:6] / ID[3:2]" and "ID[5:4] / ID[1:0]" to "ID7_4_D3_0"
– Changed field "ID[3:0]/DATA[15:12]" to "ID3_0_DATA15_12"
In Section 1.3.2.18, Channel 'n' Clock Control Register (n = 0 to (CH-1))
(CHn_CLK_CTRL), added note "The value provided..." to "CM_PRSC"
field description
Section 1.3.2.20, Channel 'n' Configuration Register (n = 0 to (CH-1))
(CHn_CONFIG): in "FIL_CNT" field description, changed expression
"This indicates the number" to "This indicates twice the number"
In Figure 28 (Enhanced Serial Message with 4-bit ID
[15:12]" to "Data Field [15:12]"
Section 1.4.1, Initialization sequence: added note "When configuring the
Single Edge Nibble Transmission (SENT)..."
Section 1.4.5, Adjustment for variation in sensor (Tx)
ambient temperatures above 114 degree C..."
In Section 1.4.6, Input programmable filter, added value of FIL_CNT in
sentence "A timing diagram of the input filter when FIL_CNT is 4 ..."
Section 1.4.7.5, CRC check: added note "The Single Edge Nibble
Transmitter (SENT) Receiver..."
Section 1.4.7.6, Pause pulse diagnostic: substantial changes
Rev 3
In Section 1.4.8, Time stamp
(cont'd)
60 to 59 when the high frequency receiver clock is 60 MHz
Chapter 50, LINFlexD
Throughout chapter: reorganized bitmaps to change array of fields to single
field for selected registers; Changed relationship for baud rate
calculation from "LIN_CLK > PBRIDGEx_CLK > 1/3*LIN_CLK" to
"(2/3)*LIN_CLK > PBRIDGEx_CLK > 1/3*LIN_CLK".
Updated Figure 1 (Block diagram)
Section 1.3.2.5.1, Header
"LINCR1 = 0"
Section 1.3.2.5.6, Timeout
LINFlexD_LINTCSR[CNT]" to the end of the bullet list item relative to
Case 2 "At the end of the ID..."
Section 1.3.2.5.7,
2nd, 3rd, and 4th samples..." to "When OSR = 8, majority of 4th, 5th, and
6th samples..."
In Section 1.3.2.5.6, Timeout
In Figure 9 (Incomplete response (for example, missing
Figure 10 (No
In Section 1.3.4.7, UART
which ..." and "When the FIFO is full, a read to..."
Table 19: LINCR1 field
"SLEEP" and "INIT"
Section 1.4.2.2, LIN Interrupt enable register
relative to bit 28 to "DBEIE_TOIE" (was "DBIE/TOIE")
DocID027809 Rev 4
Changes
(DATA_CTRL1): added note
logic, changed required prescaler value from
error: in Case 2, changed "LINCR1 = 1" to
error: added expression "+
Noise: changed paragraph "When OSR = 8, majority of
error, replaced "ocr_1" with "ocr_2"
response), replaced "OCR1" with "OCR2"
transmitter, added notes "Invalid writes to BDRL
descriptions: updated descriptions of fields
Revision history
field), changed "Data
clock: added note "At
checksum)), and
(LINIER): renamed field
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