STMicroelectronics SPC572L series Reference Manual page 2044

Revision history
Date
03-Apr-2013
2044/2058
Table 1150. Revision history(Continued)
Rev
Figure 1314 (SPU register
(CCOMS) and Counter Capture Status (CCAPS) register names
Section 61.10.1.6, SLU status (SS)
EM0); bit 22 set to EM2 (was reserved)
Table 1332: SPU action
– From client group counter bit: counter ID 00000 set to reserved (was
CPU0); counter ID 00010 set to CPU2 (was reserved); counter IDs
10000 and 10001 set to reserved (was NXMC1,2)
– From client group action bit: removed PMC1,2,3,4 and reference to
PMC in comments for action IDs 0101 to 1000
– From client group enable bit: removed reference to PMC
– From system group action bit: removed Timestamp0,1_1,2 and
references to AHB in comments for action IDs 0011 to 0110
Section 61.10.1.9.5, Trace group configuration registers (DTMGC,
PTMGC, OTMGC and
set to CPU2 (was reserved)
Section 61.10.1.10, Counters control n (CCTRLn) registers spu_cntr[0-
15]_cntrl_reg (SPU Counter[0-15] Control
reference from register name to maintain the naming consistency
Section 61.10.1.11, Counters compare n (CCMPn) registers spu_cntr[0-
15]_cmpr_reg (SPU Counter[0-15] Compare
reference from register name
Section 61.10.1.12.1, Counter compare status
explaining when w1c should be performed
Added Section 61.6.8, Format for CKSRC & CKDATA Values
Table 1339: CCTRLn register field
2
mapping of the PMC inputs with the counters is shown in Figure 1426."
(cont'd)
from description of field COUNT_INCR
Table 1340: CCMPn register field descriptions
changed table title (was CCTRLn...)
Chapter 68: Development Trigger Semaphore
Chapter 63, Nexus Aurora Router (NAR): unchanged
66: e200z215An3 Nexus 3
Chapter 65, GTM Development Interface (GTMDI)
Section 65.4.1.1, Device identity register (DID): updated contents of
bits 11–1
Chapter 1: Register Protection (REG_PROT)
Section 1.4.2.4, Global Configuration Register
Chapter 67, Password and Device Security Module (PASS)
Section 67.3, Memory map and register definition: changed "Chip Select
(CS[14:0])" to "Client Select (CS[14:0])"
Table 1157 (PASS memory map):
– Changed title (was Module memory map)
– Changed Challenge Status Register abbreviation to CHSTAT (was
CSTAT) and added its reset value
– Removed "Censorship", "Production Disable" and "Clock Jitter Enable"
rows
DocID027809 Rev 4
Changes
summary): corrected Counter Compare Status
register: bit 20 set to reserved (was
decoder:
WTMGC): bit 0 set to reserved (was CPU0); bit 2
Register): removed Timer
Registers): removed Timer
(CCOMS): added note
descriptions: removed sentence "The
spu_cntr[0-23]_cmpr_reg:
(DTS): unchanged
Module: no substantial changes
(GCR): updated introduction
RM0400