STMicroelectronics SPC572L series Reference Manual page 2056

Revision history
Date
26-Sep-2017
2056/2058
Table 1150. Revision history(Continued)
Rev
Table 40: PIT1 memory map
map)
Table 41: PIT0 memory map
map)
Table 53: Boot header
– Updated the table.
– Removed table "Boot header configuration field description"
Chapter 7: Reset and Boot
Section 7.2.2.1: Destructive
escalation....".
Chapter 8: Device Configuration Format (DCF) Records
Table 71: DCF client
Chapter 12: Core e200z215An3 description
Figure 50: Machine State Register
Table 96: MSR field
Chapter 21: Clocking
Figure 178: CMU0 block
f
CLKMT0_RMN
Chapter 22: PLL Digital Interface (PLLDIG)
Rev 4
Section 22.5.2.3: PLL Divider Register
(cont'd)
RFDPHI1).
Section 22.6.2: Clock
equation
Removed all instances of PLL1.
Chapter 24: Clock Generation Module (MC_CGM)
Figure 214: Auxiliary Clock 11 Select Control Register
Updated the reset value.
Chapter 28: Flash memory controller (PFLASH Controller)
Section 28.4.1.4: PFlash Calibration Remap Control Register
Updated the description for SAFE_CAL field.
Section 28.5.13.3: On-Chip Overlay RAM Feedback
Removed text "If a mismatch...."
Chapter 29: Embedded Flash Memory (MP55)
Section 29.3.2.13: Test Mode Disable Password Check register
Deleted text between brackets "Test Mode Disable Override Passcode
at address offset 0x3DC8"
Table 322: TMD field
reversed..."
Chapter 35: Sigma-Delta Analog-to-Digital Converter (SDADC) Digital
Interface
Reformatted
DocID027809 Rev 4
Changes
renamed (was earlied titled PIT0 memory
renamed (was earlied titled PIT1 memory
structure:
resets: Removed the bullet point "Reset
list: Removed all rows of STCU.
(MSR): Updated the figure.
descriptions: Updated the table with new fields.
diagram: Removed text "f
/4" from "CLKMN1 Supervisor" block.
configuration: Updated the "VCO frequency"
descriptions: Added Note "PWD bitfield is byte-
Figure 315: Module Configuration Register (MCR)
<
CLKMN1
(PLLDV): Removed text "RFDPHI,
(CGM_AC11_SC):
(PFCRCR):
Check:
RM0400
(TMD):