STMicroelectronics SPC572L series Reference Manual page 2052

Revision history
Date
27-Feb-2015
2052/2058
Table 1150. Revision history(Continued)
Rev
Section 48.3.17, DSPI DSI Configuration Register 1
– Renamed field "TSBCNT[5:0]" to "TSBCNT"
– Updated field "TSBCNT" width from 6 to 5 to encompass bits 3–7
– Set bit 2 to Reserved
– Updated the access value of field "DSI64E" from RW to RO
Section 48.5.3.4, DSI
request" and "and RSER[DDIF_DIRS]"
Figure 723 (DSI serialization
Registers 0-3 block from diagram
Section 48.5.9.1, MSC Dual Receiver Support with PCS
note "When using Dual receiver support, it must be ensured..."
Table 799: Interrupt and DMA request
Data Match" changed Request Type DMA to "—" (was Yes)
Section 48.5.13, Power saving
Mode..."
Section 48.5.13.1, Stop mode (External Stop
DSPI block is configured in Slave mode..."
Chapter 47, LVDS Fast Asynchronous Serial Transmission (LFAST) –
Interprocessor Communications
Removed reference to 312/320 MHz from entire chapter and referred to as
high data rate.
Section 50.6.2.15, LVDS Control Register
– Field "LVRXOP" (bits 26–28) is now split into 3 individual bits:
LVRXOP_TR (bit 26), Reserved (bit 27), and "LVRXOP_BR" (bit 28)
Rev 3
– Swapped the binary combination descriptions of field "LVRXOP_TR"
(cont'd)
– Updated field description "LVCKSS"
Section 50.7.7.1.2, Data
"MCR[TXEN]" to "MCR[RXEN]".
Chapter 48, Fast Ethernet Controller (FEC): unchanged
Chapter 1: SENT Receiver (SRX)
Throughout chapter:
– In register description sections of selected registers, changed note "The
following register figure..." to "Reads of bits beyond those for the
supported number..."
– Removed references to "SRX_DATA_CTRL2" register
In Section 1.1.1, Features, changed bulleted list item "Supports
compensation ... for drift and jitter in the Transmr clocks per channel" to
"Supports compensation... for drift in the Transmitter and Receiver
clocks per channel"
In Section 1.1.2.2, Low power modes, added two notes: "If the SOC
requests entry to debug or stop mode..." and "The message read
registers..."
In Section 1.3.2.1, Global Control Register (GBL_CTRL)
– Added field "NIB_LEN_VAR_LIMIT" at bit 15
– Updated binary combination descriptions of field "TSPRSC"
Section 1.3.2.4, Fast Message Ready Status Register
added note "These bits are either "write 1 to clear" (w1c) or self-
clearing..." in "F_RDYn" field description.
DocID027809 Rev 4
Changes
deserialization: removed expressions "or DMA
diagram): removed Parallel Input Select
conditions: In row "DSI Deserialized
features: added note "When in Slave
Mode): added paragraph "If a
(LCR):
receive: in the first paragraph, changed
RM0400
(DSPI_DSICR1):
Switchover: added
(FMSG_RDY):