ARM Cortex-M0 Technical Reference Manual

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Cortex

-M0

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Revision: r0p0

Technical Reference Manual

ARM DDI 0432C (ID112415)

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Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 5: Table Of Contents
About the programmers model ..............3-2 Modes of operation and execution .............. 3-3 Instruction set summary ................3-4 Memory model .................... 3-9 Processor core registers summary ............3-11 ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 6 Nested Vectored Interrupt Controller About the NVIC ................... 5-2 NVIC register summary ................5-3 Chapter 6 Debug About debug ....................6-2 Debug register summary ................6-9 Appendix A Revisions Glossary Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C Non-Confidential ID112415...
Page 7 Table 4-2 CPUID bit register assignments ................4-4 Table 5-1 NVIC registers ......................5-3 Table 6-1 Cortex-M0 ROM table identification values ............... 6-4 Table 6-2 Cortex-M0 ROM table components ................6-4 Table 6-3 SCS identification values ..................6-5 Table 6-4 DWT identification values ..................
Page 9: List Of Figures
List of Figures Cortex-M0 Technical Reference Manual Figure 2-1 Functional block diagram ..................2-2 Figure 4-1 CPUID bit register assignments ................4-4 Figure 6-1 CoreSight discovery ....................6-3 ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 11 Preface This preface introduces the Cortex-M0 Technical Reference Manual. It contains the following sections: • About this book on page xii • Feedback on page xv. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 12: Preface
Preface About this book This book is for the Cortex-M0 processor. Product revision status The rnpn identifier indicates the revision status of the product described in this manual, where: Identifies the major revision of the product. Identifies the minor revision or modification status of the product.
Page 13 Denotes language keywords when used outside example code. monospace bold Additional reading This section lists publications by ARM and by third parties. for access to ARM documentation. http://infocenter.arm.com ARM publications This book contains information that is specific to the processor. See the following documents for other relevant information: •...
Page 14 Note A Cortex-M0 implementation can include a Debug Access Port (DAP). This DAP is defined in v5.1 of the ARM Debug interface specification, or in the errata document to Issue A of the ARM Debug Interface v5 Architecture Specification. •...
Page 15: Feedback
Preface Feedback ARM welcomes feedback on the processor and its documentation. Feedback on the processor If you have any comments or suggestions about this product, contact your supplier giving: • The product name. • The product revision or version. •...
Page 17: Introduction
Chapter 1 Introduction This chapter introduces the Cortex-M0 processor and its features. It contains the following sections: About the processor on page 1-2 • Features on page 1-3 • Interfaces on page 1-4 • Configurable options on page 1-5 •...
Page 18: About The Processor
Introduction About the processor The Cortex-M0 processor is a very low gate count, highly energy efficient processor that is intended for microcontroller and deeply embedded applications that require an area optimized processor. Copyright © 2009 ARM Limited. All rights reserved.
Page 19: Features
• Serial Wire Debug reduces the number of pins required for debugging. For information about Cortex-M0 architectural compliance, see the Architecture and protocol information on page 1-8. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved.
Page 20: Interfaces
Introduction Interfaces The interfaces included in the processor for external access include: • external AHB-Lite interface Debug Access Port (DAP). • Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C Non-Confidential ID112415...
Page 21: Configurable Options
• as a 32-cycle iterative multiplier. The iterative multiplier has no impact on interrupt response time because the processor abandons multiply operations to take any pending interrupt. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 22: Product Documentation, Design Flow And Architecture
• The processes to sign off the integration and implementation of the design. The ARM product deliverables include reference scripts and information about using them to implement your design. Reference methodology documentation from your EDA tools vendor complements the IIM.
Page 23 They can also limit the options available to the software. Software configuration The programmer configures the processor by programming particular values into registers. This affects the behavior of the processor. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 24 The system bus of the processor implements AMBA-3 AHB-Lite. See the ARM AMBA 3 AHB-Lite Protocol Specification. Debug Access Port architecture The Debug Access Port (DAP) is an optional component, defined by v5.1 of the ARM Debug interface specification, see the ARM Debug Interface v5 Architecture Specification.
Page 25: Product Revisions
Introduction Product revisions This section describes the differences in functionality between product revisions. r0p0 First release. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 27: Chapter 2 Functional Description
Functional Description This chapter provides an overview of the processor functions. It contains the following sections: About the functions on page 2-2 • Interfaces on page 2-4. • ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 28: About The Functions
Functional Description About the functions The Cortex-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processors.
Page 29 Bus interfaces: — single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory — single 32-bit slave port that supports the DAP. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 30: Interfaces
For more information on: • DAP, see the ADI v5.1 version of the ARM Debug Interface v5, Architecture Specification • CoreSight DAP, see the ARM CoreSight Components Technical Reference Manual.
Page 31: Programmers Model
Modes of operation and execution on page 3-3 • Instruction set summary on page 3-4 • Memory model on page 3-9 • Processor core registers summary on page 3-11 • Exceptions on page 3-12. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 32: About The Programmers Model
About the programmers model The ARMv6-M ARM provides a complete description of the programmers model. This chapter gives an overview of the Cortex-M0 programmers model that describes the implementation-defined options. It also contains the ARMv6-M Thumb instructions it uses and their cycle counts for the processor. In addition: •...
Page 33: Modes Of Operation And Execution
See the ARMv6-M Architecture Reference Manual for information about the modes of operation and execution. Note Other ARM architectures support the concept of privileged or unprivileged software execution. This processor does not support different privilege levels. Software execution is always privileged, meaning software can access all the features of the processor.
Page 34: Instruction Set Summary
16-bit Thumb instructions from ARMv7-M excluding CBNZ • the 32-bit Thumb instructions Table 3-1 shows the Cortex-M0 instructions and their cycle counts. The cycle counts are based on a system with zero wait-states. Table 3-1 Cortex-M0 instruction summary Operation...
Page 35 Byte, immediate offset LDRB Rd #<imm> Word, register offset LDR Rd Halfword, register offset LDRH Rd Signed halfword, register offset LDRSH Rd Byte, register offset LDRB Rd ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 36: Operation Description
With exchange BX Rm With link and exchange BLX Rm Extend Signed halfword to word SXTH Rd Signed byte to word SXTB Rd Unsigned halfword UXTH Rd Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C Non-Confidential ID112415...
Page 37 Cycle count depends on core and debug configuration. f. Excludes time spent waiting for an interrupt or event. g. Executes as NOP. See the ARMv6-M ARM for more information about the ARMv6-M Thumb instructions ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved.
Page 38 Cortex-M profile processors. You can move software, including system level software, from the Cortex-M0 to other Cortex-M profile processors. To ensure a smooth transition, ARM recommends that code designed to operate on other Cortex-M profile processor architectures obey the following rules and configure the Configuration Control Register (CCR) appropriately: •...
Page 39: Memory Model
0x40000000 0x5FFFFFFF 0x20000000 0x3FFFFFFF 0x00000000 0x1FFFFFFF a. Space reserved for Cortex-M0 NVIC and debug components. b. Cortex-M1 devices implementing data Tightly-Coupled Memories (TCMs) in this region do not support code execution from the data TCM. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved.
Page 40 Regions not marked as suitable for code behave as Execute-Never (XN) and generate a HardFault exception if code attempts to execute from this location. See the ARMv6-M ARM for more information about the memory model. 3-10 Copyright © 2009 ARM Limited. All rights reserved.
Page 41: Processor Core Registers Summary
CONTROL The CONTROL register controls the stack used when the processor is in Thread mode. Note See the ARMv6-M ARM for information about the processor core registers and their addresses, access types, and reset values. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved.
Page 42: Exceptions
If this is done, the highest priority interrupt is jitter-free. See the documentation supplied by the processor implementer for more information. To reduce interrupt latency and jitter, the Cortex-M0 processor implements both interrupt late-arrival and interrupt tail-chaining mechanisms, as defined by the ARMv6-M architecture.
Page 43: Chapter 4 System Control
This chapter summarizes the system control registers and their structure. It contains the following sections: • About system control on page 4-2 • System control register summary on page 4-3. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 44: About System Control
System Control About system control This section describes the system control registers that control and configure various system control functions. Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C Non-Confidential ID112415...
Page 45: System Control Register Summary
SYST_RVR, SYST_CVR, and SYST_CALIB register reads as zero, writes ignored RAZ/WI. • See the ARMv6-M ARM for more information about the system control registers, and their addresses and access types, and reset values not shown in Table 4-1. ARM DDI 0432C Copyright ©...
Page 46: Table 4-2 Cpuid Bit Register Assignments
0xC20 [3:0] Revision Indicates revision. In ARM implementations this is the minor revision number n in the pn part of the rnpn revision status, see Product revision status on page xii. For example, for release r0p0: Copyright © 2009 ARM Limited. All rights reserved.
Page 47: Chapter 5 Nested Vectored Interrupt Controller
This chapter summarizes the Nested Vectored Interrupt Controller (NVIC). It contains the following sections: • About the NVIC on page 5-2 • NVIC register summary on page 5-3. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 48: About The Nvic
About the NVIC External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority of each interrupt. The NVIC and the Cortex-M0 processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts.
Page 49: Nvic Register Summary
Interrupt Clear-Pending Register in the ARMv6-M ARM IPR0-IPR7 Interrupt Priority Registers in the ARMv6-M ARM Note See the ARMv6-M ARM for more information about the NVIC registers and their addresses, access types, and reset values. ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved.
Page 51: Chapter 6 Debug
Chapter 6 Debug This chapter summarizes the debug system. It contains the following sections: About debug on page 6-2 • Debug register summary on page 6-9. • ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 52: About Debug
The processor implementation can be partitioned to place the debug components in a separate power domain from the processor core and NVIC. When debug is implemented, ARM recommend that a debugger identifies and connects to the debug components using the CoreSight debug infrastructure.
Page 53 A debugger cannot rely on the Cortex-M0 ROM table being the first ROM table encountered. One or more system ROM tables are required between the access port and the Cortex-M0 ROM table if other CoreSight components are in the system, or if the implementation is uniquely identifiable.
Page 54: Table 6-2 Cortex-M0 Rom Table Components
Component ID1 0x00000010 Component ID2 0x00000005 Component ID3 0x000000B1 Table 6-2 shows the CoreSight components that the Cortex-M0 ROM table points to. The values depend on the implemented debug configuration. Table 6-2 Cortex-M0 ROM table components Component Value Description See System Control Space on page 6-5...
Page 55: Table 6-3 Scs Identification Values
SCS CoreSight identification Table 6-3 shows the SCS CoreSight identification registers and values for debugger detection. Final debugger identification of the Cortex-M0 processor is through the CPUID register in the SCS, see CPUID Register on page 4-4. Table 6-3 SCS identification values...
Page 56: Table 6-4 Dwt Identification Values
Debug 6.1.3 Data watchpoint unit The Cortex-M0 DWT implementation provides zero, one or two watchpoint register sets. A processor configured with zero watchpoint implements no watchpoint functionality and the ROM table shows that no DWT is implemented. DWT functionality The processor watchpoints implement both data address and PC based watchpoint functionality, a PC sampling register, and support comparator address masking, as described in the ARMv6-M ARM.
Page 57: Table 6-5 Bpu Identification Registers
DWT Program Counter Sample Register (DWT_PCSR). This register permits a debugger to periodically sample the PC without halting the processor. This provides coarse grained profiling. See the ARMv6-M ARM for more information. The Cortex-M0 DWT_PCSR records both instructions that pass their condition codes and those that fail. 6.1.4...
Page 58 Debug See the ARMv6-M ARM and the ARM CoreSight Components Technical Reference Manual for more information about the BPU CoreSight identification registers, and their addresses and access types. Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C Non-Confidential...
Page 59: Debug Register Summary
Description DFSR Debug Fault Status Register in the ARMv6-M ARM DHCSR Debug Halting Control and Status Register in the ARMv6-M ARM DCRSR Debug Core Register Selector Register in the ARMv6-M ARM DCRDR Debug Core Register Data Register in the ARMv6-M ARM...
Page 60 DWT_MASK1 Function Register in the ARMv6-M ARM DWT_FUNCTION1 Note See the ARMv6-M ARM for more information about the debug registers and their addresses, access types, and reset values. 6-10 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C...
Page 61: Table A-1 Issue A
Update to the instruction set summary Instruction set summary on page 3-4 All revisions Clarification of the processor core register set summary Processor core registers summary on All revisions page 3-11 ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. ID112415 Non-Confidential...
Page 62: Table A-3 Differences Between Issue B And Issue C
Revisions Table A-3 Differences between issue B and issue C Change Location Affects No technical changes Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C Non-Confidential ID112415...
Page 63 A family of protocol specifications that describe a strategy for the interconnect. AMBA is the ARM open standard for on-chip buses. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC).
Page 64 Breakpoints can be removed after the program is successfully tested. See also Watchpoint. An 8-bit data item. Byte Glossary-2 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C Non-Confidential ID112415...
Page 65 The ARM architecture supports byte-invariant systems in ARMv6 and later versions. A core is that part of a processor that contains the ALU, the datapath, the...
Page 66 These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as 0 and read as 0. Glossary-4 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C Non-Confidential ID112415...
Page 67 JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is TRST. A halfword that specifies an operation for an ARM processor in Thumb state to Thumb instruction perform. Thumb instructions must be halfword-aligned.

ARM Cortex-M0 Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Functional Description

Chapter 3 Programmers Model

Chapter 4 System Control

Chapter 5 Nested Vectored Interrupt Controller

Chapter 6 Debug

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