C10.2 Performance Monitors Control Register - ARM Cortex-A35 Technical Reference Manual

C10.2 Performance Monitors Control Register
The PMCR characteristics are:
Purpose
Usage constraints
Configurations
Attributes
IMP, [31:24]
IDCODE, [23:16]
N, [15:11]
[10:7]
LC, [6]
100236_0100_00_en
Provides details of the Performance Monitors implementation, including the number of counters
implemented, and configures and controls the counters.
This register is accessible as follows:
This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.
PMCR is architecturally mapped to AArch64 PMCR_EL0 register. See
Monitors Control Register, EL0 on page
PMCR[6:0] is architecturally mapped to external PMCR_EL0 register.
There is one copy of this register that is used in both Secure and Non-secure states.
PMCR is a 32-bit register.
31 24 23
IMP
Implementer code:
Arm.
0x41
This is a read-only field.
Identification code:
Cortex‑A35.
0x0A
This is a read-only field.
Number of event counters.
Six counters.
0b00110
Reserved, .
RES0
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
EL0 EL0 EL1 EL1
(NS) (S) (NS) (S)
Config Config RW RW RW RW
C10-704.
16 15
IDCODE
reserved.
Non-Confidential
C10 PMU registers

C10.2 Performance Monitors Control Register

EL2 EL3
EL3
(SCR.NS = 1) (SCR.NS = 0)
RW
C10.6 Performance
11 10 7 6 5 4 3 2 1 0
N 0 LC DP X D C P
RES
Figure C10-1 PMCR bit assignments
E
C10-692