External Bus Control - Renesas M16C/64A Series User Manual

M16C/64A Group
11.3.5

External Bus Control

The following describes the signals needed for accessing external devices and the functionality of
software wait states.
11.3.5.1 Address Bus
The address bus consists of 20 lines: A0 to A19. The address bus width can be set to 12, 16, or 20
bits using the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register. Table 11.5 lists the
Set Value of Bits PM06 and PM11 and the Corresponding Address Bus Widths.
Table 11.5 Set Value of Bits PM06 and PM11 and the Corresponding Address Bus Widths
Bit Set Value
PM11 = 1
PM06 = 1
PM11 = 0
PM06 = 1
PM11 = 0
PM06 = 0
Note:
1. Only set the values listed above.
When the processor mode is changed from single-chip mode to memory expansion mode, the
address bus is undefined until an external area is accessed.
11.3.5.2 Data Bus
When input to the BYTE pin is high (8-bit width), the data bus is comprised of eight lines (D0 to D7).
When input to the BYTE pin is low (16-bit width), the data bus is comprised of 16 lines (D0 to D15).
Do not change the input level to the BYTE pin.
11.3.5.3 Chip Select Signal
The chip select signals (hereafter referred to as CS ) are output from the CSi pin (i = 0 to 3). These
pins can be set to function as I/O ports or as CS using the CSi bit in the CSR register.
In 1-MB mode, the external area can be separated into a maximum of four spaces by the CSi signal.
In 4-MB mode, the CSi signal or bank number is output from the CSi pin. Refer to 12. "Memory Space
Expansion Function". Figure 11.2 shows Examples of Address Bus and CSi Signal Output in 1-MB
Mode.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
(1)
P3_4 to P3_7
P4_0 to P4_3
P4_0 to P4_3
Pin Function
A12 to A15
A12 to A15
A16 to A19
11. Bus
Address Bus Width
12 bits
16 bits
20 bits
Page 144 of 800