Texas Instruments OMAP5912 Reference Manual page 1685

SPI Operation Using the Clock Stop Mode
Table 11. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
6.4 Clock Stop Mode Timing Diagrams
74 Multichannel Buffered Serial Ports (McBSPs)
Bit Settings
CLKSTP = 00b or 01b
CLKXP = 0 or 1
CLKRP = 0 or 1
CLKSTP = 10b
CLKXP = 0
CLKRP = 0
CLKSTP = 11b
CLKXP = 0
CLKRP = 1
CLKSTP = 10b
CLKXP = 1
CLKRP = 0
CLKSTP = 11b
CLKXP = 1
CLKRP = 1
The timing diagrams for the four possible clock stop mode configurations are
shown here. Notice that the frame-synchronization signal used in clock stop
mode is active throughout the entire transmission as a slave-enable signal.
Although the timing diagrams show 8-bit transfers, the packet length can be
set to 8, 12, 16, 20, 24, or 32 bits per packet. The receive packet length is
selected with the RWDLEN1 bits of RCR1, and the transmit packet length is
selected with the XWDLEN1 bits of XCR1. For clock stop mode, the values of
RWDLEN1 and XWDLEN1 must be the same because the McBSP transmit
and receive circuits are synchronized to a single clock.
Note:
Even if multiple words are consecutively transferred, the CLKX signal is al-
ways stopped and the FSX signal returns to the inactive state after a packet
transfer. When consecutive packet transfers are performed, this leads to a
minimum idle time of two bit-periods between each packet transfer.
Clock Scheme
Clock stop mode disabled. Clock enabled for non-SPI
mode.
Low inactive state without delay: The McBSP transmits
data on the rising edge of CLKX and receives data on
the falling edge of CLKR.
Low inactive state with delay: The McBSP transmits
data one-half cycle ahead of the rising edge of CLKX
and receives data on the rising edge of CLKR.
High inactive state without delay: The McBSP transmits
data on the falling edge of CLKX and receives data on
the rising edge of CLKR.
High inactive state with delay: The McBSP transmits
data one-half cycle ahead of the falling edge of CLKX
and receives data on the falling edge of CLKR.
SPRU762B