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SPI Operation Using the Clock Stop Mode
6.7
McBSP as an SPI Slave
Figure 43.
SPI Interface With McBSP as Slave
80
Multichannel Buffered Serial Ports (McBSPs)
The McBSP can also provide a slave-enable signal (SS_) on the FSX pin. If
a slave-enable signal is required, the FSX pin must be configured as an output
and the transmitter must be configured so that a frame-synchronization pulse
is generated automatically each time a packet is transmitted (FSGM = 0). The
polarity of the FSX pin is programmable high or low; however, in most cases
the pin must be configured active low.
When the McBSP is configured as described for SPI-master operation, the bit
fields for frame-synchronization pulse width (FWID) and frame-synchronization
period (FPER) are overridden, and custom frame-synchronization waveforms
are not allowed. To see the resulting waveform produced on the FSX pin, see
the timing diagrams in section 6.4. The signal becomes active before the first
bit of a packet transfer, and remains active until the transfer of the last bit of
the packet. After the packet transfer is complete, the FSX signal returns to the
inactive state.
An SPI interface with the McBSP used as a slave is shown in Figure 43. When
the McBSP is configured as a slave, DX is used as the MISO signal and DR
is used as the MOSI signal.
McBSP slave
The register bit values required to configure the McBSP as a slave are listed
in Table 13. Following the table are more details about configuration
requirements.
SPI-compliant
master
CLKX
SCK
DX
MISO
DR
MOSI
FSX
SS
SPRU762B
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