Texas Instruments OMAP5912 Reference Manual page 1690

Multimedia processor device overview and architecture
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Table 12. Bit Values Required to Configure the McBSP as an SPI Master
SPRU762B
Required Bit Setting
CLKSTP = 10b or 11b
CLKXP = 0 or 1
CLKRP = 0 or 1
CLKXM = 1
SCLKME = 0
CLKSM = 1
CLKGDV is a value
from 0 to 255
FSXM = 1
FSGM = 0
FSXP = 1
XDATDLY = 01b
RDATDLY = 01b
When the McBSP functions as the SPI master, it controls the transmission of
data by producing the serial clock signal. The clock signal on the CLKX pin is
enabled only during packet transfers. When packets are not being transferred,
the CLKX pin remains high or low depending on the polarity used.
For SPI master operation, the CLKX pin must be configured as an output. The
sample rate generator is then used to derive the CLKX signal from the CPU
clock. The clock stop mode internally connects the CLKX pin to the CLKR
signal so that no external signal connection is required on the CLKR pin and
both the transmit and receive circuits are clocked by the master clock (CLKX).
The data delay parameters of the McBSP (XDATDLY and RDATDLY) must be
set to 1 for proper SPI master operation. A data delay value of 0 or 2 is
undefined in the clock stop mode.
SPI Operation Using the Clock Stop Mode
Description
The clock stop mode (without or with a clock delay) is
selected.
The polarity of CLKX as seen on the CLKX pin is positive
(CLKXP = 0) or negative (CLKXP = 1).
The polarity of CLKR as seen on the CLKR pin is
positive (CLKRP = 0) or negative (CLKRP = 1).
The CLKX pin is an output pin driven by the internal
sample rate generator. Because CLKSTP is equal
to 10b or 11b, CLKR is driven internally by CLKX.
The clock generated by the sample rate generator
(CLKG) is derived from the CPU clock.
CLKGDV defines the divide down value for CLKG.
The FSX pin is an output pin driven according to the
FSGM bit.
The transmitter drives a frame-synchronization pulse
on the FSX pin every time data is transferred from DXR1
to XSR1.
The FSX pin is active low.
This setting provides the correct setup time on the FSX
signal.
Multichannel Buffered Serial Ports (McBSPs)
79

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