Texas Instruments OMAP5912 Reference Manual page 1684

Table 10. Bits Used to Enable and Configure the Clock Stop Mode
SPRU762B
Bit Field
CLKSTP bits of SPCR1
CLKXP bit of PCR
CLKRP bit of PCR
CLKXM bit of PCR
XPHASE bit of XCR2
RPHASE bit of RCR2
XFRLEN1 bits of XCR1
RFRLEN1 bits of RCR1
XWDLEN1 bits of XCR1
RWDLEN1 bits of RCR1
SPI Operation Using the Clock Stop Mode
Description
Use these bits to enable the clock stop mode and to
select one of two timing variations. (See also Table 11.)
This bit determines the polarity of the CLKX signal. (See
also Table 11.)
This bit determines the polarity of the CLKR signal. (See
also Table 11.)
This bit determines whether CLKX is an input signal
(McBSP as slave) or an output signal (McBSP as
master).
You must use a single-phase transmit frame
(XPHASE = 0).
You must use a
(RPHASE = 0).
You must use a transmit frame length of 1 serial word
(XFRLEN1 = 0).
You must use a receive frame length of 1 serial word
(RFRLEN1 = 0).
The XWDLEN1 bits determine the transmit packet
length. XWDLEN1 must be equal to RWDLEN1
because in the clock stop mode. The McBSP transmit
and receive circuits are synchronized to a single clock.
The RWDLEN1 bits determine the receive packet
length. RWDLEN1 must be equal to XWDLEN1
because in the clock stop mode. The McBSP transmit
and receive circuits are synchronized to a single clock.
Multichannel Buffered Serial Ports (McBSPs)
single-phase receive frame
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