Texas Instruments OMAP5912 Reference Manual page 1688

SPRU762B
Step 3: Program registers that affect SPI operation.
Program the appropriate McBSP registers to configure the McBSP
for proper operation as an SPI master or an SPI slave. For a list of
important bits settings, see one of the following topics:
McBSP as the SPI Master (section 6.6)
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McBSP as an SPI Slave (section 6.7)
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Step 4: Enable the sample rate generator.
To release the sample rate generator from reset, set the sample rate
generator reset bit (GRST = 1) in SPCR2.
Make sure that during the write to SPCR2, you only modify GRST.
Otherwise, you modify the McBSP configuration you selected in the
previous step.
Step 5: Enable the transmitter and receiver.
After the sample rate generator is released from reset, wait two sam-
ple rate generator clock periods for the McBSP logic to stabilize.
If the CPU services the McBSP transmit and receive buffers, then
you can immediately enable the transmitter (XRST = 1 in SPCR2)
and enable the receiver (RRST = 1 in SPCR1).
If the DMA controller services the McBSP transmit and receive buff-
ers, then you must first configure the DMA controller. This includes
enabling the channels that service the McBSP buffers. When the
DMA controller is ready, make XRST = 1 and RRST = 1.
In either case, make sure you only change XRST and RRST when
you write to SPCR2 and SPCR1. Otherwise, you modify the bit set-
tings you selected earlier in this procedure.
After the transmitter and receiver are released from reset, wait two
sample rate generator clock periods for the McBSP logic to stabilize.
Step 6: If necessary, enable the frame-synchronization logic of the sample
rate generator.
After the required data acquisition setup is done (DXR[1/2] is loaded
with data), set FRST = 1 if an internally generated frame-synchro-
nization pulse is required, that is, if the McBSP is the SPI master.
SPI Operation Using the Clock Stop Mode
Multichannel Buffered Serial Ports (McBSPs) 77