Functional Operation; Basic Operation; Arm Ddi 0306B - ARM PrimeCelL PL320 Technical Reference Manual

Inter-processor communications module

Table of Contents

Functional Overview

2.2

Functional operation

2.2.1

2-4

Arrow.com.

Downloaded from

The IPCM generates interrupts under software control. These interrupts normally have

data associated with them and can be directed to one or more of up to 32 different

interrupt outputs. Each interrupt output corresponds directly to a bit in every Mailbox

Source, Mailbox Destination, and Mailbox Mask Register in every mailbox in the

IPCM. These registers therefore control which interrupt lines are asserted when

messages are sent and acknowledged.

You connect the interrupt outputs to the system interrupt controllers during integration.

One or more interrupt outputs can connect to each interrupt controller. Normally the

IPCM has at least one interrupt output connected to every interrupt controller in the

system, enabling any core to send a message to any other core. When more than one

IPCM interrupt is connected to the same interrupt controller, different types of message

can be indicated on different interrupt lines, and therefore handled by different ISRs.

A multi-core system normally has at least one IPCM instantiated. More can be

instantiated if required. Because the IPCM is configurable, you can have several

differently configured IPCMs instantiated in the same system.

The operation of the IPCM is described in more detail in the following sections:

•

Basic operation

•

Channel ID on page 2-5

•

Using mailboxes on page 2-7.

Figure 2-3 on page 2-5 shows an example system in which the IPCM is integrated so

that IPCMINT[0] is connected to the interrupt controller for Core0 and IPCMINT[1]

is connected to the interrupt controller for Core1.

Table of Contents