B2.3 Aarch64 Exception Handling Registers - ARM Cortex-A35 Technical Reference Manual

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B2.3
AArch64 Exception handling registers
The following table shows the fault handling registers in AArch64 state.
Bits[63:32] are reset to
Name
Type Reset
0x00000000
AFSR0_EL1 RW
0x00000000
AFSR1_EL1 RW
ESR_EL1
RW
UNK
IFSR32_EL2 RW
UNK
0x00000000
AFSR0_EL2 RW
0x00000000
AFSR1_EL2 RW
ESR_EL2
RW
UNK
0x00000000
AFSR0_EL3 RW
0x00000000
AFSR1_EL3 RW
ESR_EL3
RW
UNK
FAR_EL1
RW
UNK
FAR_EL2
RW
UNK
0x0000000000000000 64
HPFAR_EL2 RW
FAR_EL3
RW
UNK
VBAR_EL1
RW
UNK
ISR_EL1
RO
UNK
VBAR_EL2
RW
UNK
VBAR_EL3
RW
UNK
100236_0100_00_en
for all 64-bit registers in the table.
0x00000000
Width Description
32
B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3 on page B2-391
32
B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 on page B2-392
32
B2.41 Exception Syndrome Register, EL1 on page B2-423
32
B2.69 Instruction Fault Status Register, EL2 on page B2-479
32
B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3 on page B2-391
32
B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 on page B2-392
32
B2.42 Exception Syndrome Register, EL2 on page B2-425
32
B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3 on page B2-391
32
B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 on page B2-392
32
B2.43 Exception Syndrome Register, EL3 on page B2-427
64
B2.44 Fault Address Register, EL1 on page B2-429
64
B2.45 Fault Address Register, EL2 on page B2-430
B2.49 Hypervisor IPA Fault Address Register, EL2 on page B2-440
64
B2.46 Fault Address Register, EL3 on page B2-431
64
B2.100 Vector Base Address Register, EL1 on page B2-551
32
B2.72 Interrupt Status Register, EL1 on page B2-484
64
B2.101 Vector Base Address Register, EL2 on page B2-552
64
B2.102 Vector Base Address Register, EL3 on page B2-553
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B2.3 AArch64 Exception handling registers

Table B2-2 AArch64 exception handling registers
B2 AArch64 system registers
B2-365

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