Operation - ARM ETB11 Technical Reference Manual

Functional Description

2.2

Operation

2-4

The on-chip ETB11 operates as follows:

The ETM architecture version is supplied to the Data Formatter using the

PROTOCOL[1:0] signal. This must be set to b10.

Configuration registers are set up through the TAP controller or through the AHB

interface.

Trace capture is enabled using the control register.

Trace data is continuously written into the trace RAM while the ETB11 is enabled

and the trigger counter value is nonzero. Once the ETM11RV indicates a trigger

by asserting TRIGGER, the trigger counter decrements once per word of trace

stored.

When the trigger counter reaches zero the acquisition complete flag, AcqComp,

is activated and trace capture stops. The value loaded into the trigger counter

therefore sets the number of data words stored in the trace RAM after a trigger

event.

The debugging tools through the TAP controller can read trace data stored in the

trace RAM through the TAP controller or through the AHB interface.

•

To read data through the TAP controller you must:

Disable trace capture. If trace capture is enabled when the RAM Data

Write the location that data is read from into the RAM Read Pointer

Read the RAM Data Register to return the data at the address stored

in the RAM Read Pointer Register. The read address pointer

increments after each RAM Data Register read and the next data

value is automatically read from the RAM and stored in the RAM

Data Register.

You must precede the read access by a write to the RAM Read Pointer

valid data.

•

The trace data can also be read using the AHB interface. The trace RAM is

aliased into the system memory space. This means that reading a value from

the trace RAM requires an

space. The AHB interface can also write to the ETB11 memory when trace

capture is disabled.

Note

type instruction from the trace RAM address

LDR

ARM DDI 0275D

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