Table 2-7 Cache Size Encoding (M=0); Table 2-8 Cache Associativity Encoding (M=0) - ARM ARM926EJ-S Technical Reference Manual

Programmer's Model
2-10
Assoc The Assoc field determines the cache associativity in conjunction with
the M bit.
M bit The multiplier bit determines the cache size and cache associativity
values in conjunction with the Size and Assoc fields. If the cache is
present, M must be set to 0. If the cache is absent, M must be set to 1. For
the ARM926EJ-S processor, M is always set to 0.
Len The Len field determines the line length of the cache.
The size of the cache is determined by the Size field and the M bit. The M bit is 0 for
the DCache and ICache. The Size field is bits [21:18] for the DCache and bits [9:6] for
the ICache. The minimum size of each cache is 4KB, and the maximum size is 128KB.
Table 2-7 shows the cache size encoding.
The associativity of the cache is determined by the Assoc field and the M bit. The M bit
is 0 for the DCache and ICache. The Assoc field is bits [17:15] for the DCache and bits
[5:3] for the ICache. Table 2-8 shows the cache associativity encoding.
Copyright © 2001-2003 ARM Limited. All rights reserved.

Table 2-7 Cache size encoding (M=0)

Size field
b0011
b0100
b0101
b0110
b0111
b1000

Table 2-8 Cache associativity encoding (M=0)

Assoc field
b010
Other values
Cache size
4KB
8KB
16KB
32KB
64KB
128KB
Associativity
4-way
Reserved
ARM DDI0198D