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DSTREAM-HT Getting Started Guide
Document ID: 101760_1.0_02_en
Version 1.0
The DSTREAM-HT system
2. The DSTREAM-HT system
DSTREAM-HT is a debug and trace hardware system that enables software debug and trace for the
optimization of software running on Arm
®
processor-based targets.
DSTREAM-HT provides an interface between a host such as Arm Development Studio and an
Arm processor-based target using a hardware interface such as JTAG or Serial Wire Debug (SWD).
DSTREAM-HT also enables the collection of up to six lanes of HSSTP trace for powerful code
optimization.
The DSTREAM-HT debug system is made up of a standard Arm DSTREAM-ST unit, along with an
additional Arm HSSTP probe, enabling:
• Debug on Arm processors from Armv4 to Armv8.
• USB 3.0 and remote Gigabit Ethernet host connections.
• Code download speeds of up to 12MB per second.
• JTAG clock of up to 180MHz.
• Serial Wire Debug of up to 125MHz (standard single-ended signaling).
• A wide range of target connectors.
• Up to six lane HSSTP trace support (up to 60Gbps maximum trace bandwidth).
• Up to two lanes of SETM trace.
• Flexible HSSTP lane rates of up to 12.5Gbps.
• Up to 4-bit parallel trace support (up to 2.4Gbps maximum trace bandwidth).
• Flexible DDR trace clock timing of up to 300MHz (600Mbits/s, per pin).
• 8GB of trace memory storage on the HSSTP probe.
• Support for up to 1022 CoreSight
™
devices.
• Remote target reset.
• Device bring-up and test utilities.
• Flexible architecture to support third party IP and debuggers.
For more feature information, see the
DSTREAM-HT web page
on the Arm Developer website.
For the purposes of this content:
• The term DSTREAM-ST refers only to the DSTREAM-ST unit.
• The terms DSTREAM-HT or DSTREAM-HT system refer to both the DSTREAM-ST unit and
HSSTP probe working in combination.
This chapter describes the DSTREAM-HT hardware.
Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
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