Table 8-20 System Handler Control And State Register Bit Assignment; Figure 8-14 System Handler Control And State Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
Field Name
[31:19] -
[18] USGFAULTENA
[17] BUSFAULTENA
[16] MEMFAULTENA
[15] SVCALLPENDED
[14] BUSFAULTPENDED
[13] MEMFAULTPENDED
[12] -
[11] SYSTICKACT
[10] PENDSVACT
8-28

Figure 8-14 System Handler Control and State Register bit assignments

Table 8-20 describes the fields of the System Handler Control Register.

Table 8-20 System Handler Control and State Register bit assignment

Definition
Reserved
Set to 0 to disable, else 1 for enabled.
Set to 0 to disable, else 1 for enabled.
Set to 0 to disable, else 1 for enabled.
Reads as 1 if SVCall is pended Started to invoke, but was replaced by a higher
priority interrupt.
Reads as 1 if BusFault is pended Started to invoke, but was replaced by a higher
priority interrupt.
Reads as 1 if MemManage is pended Started to invoke, but was replaced by a higher
priority interrupt.
Reserved
Reads as 1 if SysTick is active.
Reads as 1 if PendSV is active.
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