Table 8-21 System Handler Control And State Register Bit Assignments; Figure 8-15 System Handler Control And State Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
31
8-30
Reserved
USGFAULTENA
BUSFAULTENA
MEMFAULTENA
SVCALLPENDED
BUSFAULTPENDED
MEMFAULTPENDED
USGFAULTPENDED
SYSTICKACT
PENDSVACT
Reserved
MONITORACT
SVCALLACT
Reserved
USGFAULTACT
Reserved
BUSFAULTACT
MEMFAULTACT

Figure 8-15 System Handler Control and State Register bit assignments

Table 8-21 describes the bit assignments of the System Handler Control Register.

Table 8-21 System Handler Control and State Register bit assignments

Bits
[31:19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
Copyright © 2005-2008 ARM Limited. All rights reserved.
19 18 17 16 15 14
Field
-
USGFAULTENA
BUSFAULTENA
MEMFAULTENA
SVCALLPENDED
BUSFAULTPENDED
MEMFAULTPENDED
USGFAULTPENDED
SYSTICKACT
Non-Confidential
13 12 11 10 9 8 7 6
Function
Reserved
Set to 0 to disable, else 1 for enabled.
Set to 0 to disable, else 1 for enabled.
Set to 0 to disable, else 1 for enabled.
Reads as 1 if SVCall is pended.
Reads as 1 if BusFault is pended.
Reads as 1 if MemManage is pended.
Read as 1 if usage fault is pended
Reads as 1 if SysTick is active.
4 3 2 1 0
ARM DDI 0337G
Unrestricted Access