B2.18 Ccsidr_El1, Cache Size Id Register, El1 - ARM Cortex-A76 Core Technical Reference Manual

B2.18 CCSIDR_EL1, Cache Size ID Register, EL1
The CCSIDR_EL1 provides information about the architecture of the currently selected cache.
Bit field descriptions
CCSIDR_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
WT, [31]
WB, [30]
RA, [29]
WA, [28]
NumSets, [27:13]
100798_0300_00_en
31 30 29 28 27
WT WA
WB
RA
Indicates whether the selected cache level supports Write-Through:
Cache Write-Through is not supported at any level.
0
For more information about encoding, see
Indicates whether the selected cache level supports Write-Back. Permitted values are:
Write-Back is not supported.
0
Write-Back is supported.
1
For more information about encoding, see
Indicates whether the selected cache level supports read-allocation. Permitted values are:
Read-allocation is not supported.
0
Read-allocation is supported.
1
For more information about encoding, see
Indicates whether the selected cache level supports write-allocation. Permitted values are:
Write-allocation is not supported.
0
Write-allocation is supported.
1
For more information about encoding, see
(Number of sets in cache) - 1. Therefore, a value of 0 indicates one set in the cache. The number
of sets does not have to be a power of 2.
For more information about encoding, see
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B2.18 CCSIDR_EL1, Cache Size ID Register, EL1

NumSets
Figure B2-14 CCSIDR_EL1 bit assignments
CCSIDR_EL1 encodings on page
CCSIDR_EL1 encodings on page
CCSIDR_EL1 encodings on page
CCSIDR_EL1 encodings on page
CCSIDR_EL1 encodings on page
reserved.
Non-Confidential
B2 AArch64 system registers
13 12
Associativity
LineSize
B2-160.
3 2 0
B2-160.
B2-160.
B2-160.
B2-160.
B2-159