Table 11-3 Comp Mapping; Figure 11-3 Flash Patch Remap Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

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31
11-10
• COMP is the matching comparator. See Table 11-3.
• HADDR[1:0] is the two Least Significant Bits (LSBs) of the original address.
HADDR[1:0] is always 2'b00 for instruction fetches.
The register address, access type, and Reset state are:
Address 0xE0002004
Access Read/write
Reset state This register is not reset
Figure 11-3 shows the bit assignments of the Flash Patch Remap Register.
29 28
Reserved
Copyright © 2005-2008 ARM Limited. All rights reserved.
COMP[2:0]
000
001
010
011
100
101
110
111
REMAP

Figure 11-3 Flash Patch Remap Register bit assignments

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Table 11-3 COMP mapping

Comparator Description
FP_COMP0 Instruction comparator
FP_COMP1 Instruction comparator
FP_COMP2 Instruction comparator
FP_COMP3 Instruction comparator
FP_COMP4 Instruction comparator
FP_COMP5 Instruction comparator
FP_COMP6 Literal comparator
FP_COMP7 Literal comparator
5 4 0
Reserved
ARM DDI 0337G
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