Figure 1-4 Basic Jtag Port Synchronizer; Figure 1-5 Timing Diagram For The Basic Jtag Synchronizer; Figure 1-6 Jtag Port Synchronizer For Single Rising-Edge D-Type Asic Design Rules - ARM DSTREAM-PT Reference Manual

The following figure shows a partial timing diagram for the basic JTAG synchronizer. To reduce the
delay, and because the second flip-flop only provides better immunity to metastability problems, clock
the flip-flops from opposite edges of the system clock.
ASIC design rules often impose a restriction that all flip-flops in a design must be clocked by one edge
of a single clock. To interface the clocking restriction to a JTAG port that is asynchronous to the system,
you must convert the JTAG TCK events into clock enables for this single clock. You must also ensure
that the JTAG port cannot overrun this synchronization delay.
One possible implementation of this circuit, is:
TDI
RTCK
TCK
D
nCLR
nTRST
CLK
TMS
101714_0100_02_en
TMS
TDI
TDO
RTCK
TCK
nTRST
CLK
TCK
CLK
RTCK
Q D Q D Q
nCLR nCLR

Figure 1-6 JTAG port synchronizer for single rising-edge D-type ASIC design rules

Copyright © 2019 Arm Limited or its affiliates. All rights reserved.
D Q D
nCLR
nCLR

Figure 1-4 Basic JTAG port synchronizer

Figure 1-5 Timing diagram for the Basic JTAG synchronizer

TCKFalli ngEn
TCKRisingEn
Shift En
TAP Ctrl
CKEN
State
TMS
Machine
nRESET
Non-Confidential
1 Debug and trace interface
1.1 JTAG signals
TMO
TDI
TDO
ASIC
Q TCK
nTRST
CLK
CKEN
D
OUT
IN
Scan
CKEN
Chain
TDO
Q
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