B1.99 Normal Memory Remap Register - ARM Cortex-A35 Technical Reference Manual

B1.99 Normal Memory Remap Register
The NMRR characteristics are:
Purpose
Usage constraints
Configurations
Attributes
ORn, [2n+17:2n+16]
IRn, [2n+1:2n]
100236_0100_00_en
Provides additional mapping controls for memory regions that are mapped as Normal memory
by their entry in the PRRR.
This register is accessible as follows:
The register is:
• Used in conjunction with the PRRR.
• Not accessible when using the Long-descriptor translation table format.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
If EL3 is using AArch32, write access to NMRR(S) is disabled when the CP15SDISABLE2
signal is asserted HIGH.
The Non-secure NMRR is architecturally mapped to the AArch64 MAIR_EL1[63:32] register
when TTBCR.EAE==0. See
The Secure NMRR is mapped to the AArch64 MAIR_EL3[63:32] register when
TTBCR.EAE==0. See B2.79 Memory Attribute Indirection Register, EL3 on page
NMRR is a 32-bit register when TTBCR.EAE is 0.
31 30 29 28 27 26 25 24 23
OR7 OR6 OR5 OR4 OR3 OR2
Outer Cacheable property mapping for memory attributes n, where n is 0-7, if the region is
mapped as Normal memory by the PRRR.TRn entry. n is the value of the TEX[0], C and B bits,
see Memory attributes and the n value for the PRRR field descriptions on page
possible values of this field are:
Region is Non-cacheable.
0b00
Region is Write-Back, Write-Allocate.
0b01
Region is Write-Through, no Write-Allocate.
0b10
Region is Write-Back, no Write-Allocate.
0b11
Inner Cacheable property mapping for memory attributes n, where n is 0-7, if the region is
mapped as Normal Memory by the PRRR.TRn entry. n is the value of the TEX[0], C and B bits,
see Memory attributes and the n value for the PRRR field descriptions on page
possible values of this field are the same as those given for the ORn field.
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
EL0 EL0 EL1 EL1
(NS) (S) (NS) (S)
- - RW RW RW RW
B2.77 Memory Attribute Indirection Register, EL1 on page
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR1 OR0 IR7
reserved.
Non-Confidential
B1 AArch32 system registers

B1.99 Normal Memory Remap Register

EL2 EL3
EL3
(SCR.NS = 1) (SCR.NS = 0)
RW
B2-499.
IR6 IR5 IR4 IR3 IR2
Figure B1-53 NMRR bit assignments
B1-323. The
B1-323. The
B2-496.
IR1 IR0
B1-319