Table B-11 Memory Region Remap Register Instructions; Figure B-9 Memory Region Remap Register Format - ARM ARM926EJ-S Technical Reference Manual

B.1.7 Memory Region Remap Register
31
ARM DDI0198D
Table B-10 MMU Debug Control Register bit assignments (continued)
Bit Name Function
[3] DIUTM Disable instruction micro TLB match
[2] DDUTM Disable data micro TLB match
[1] DIUTL Disable instruction micro TLB load
[0] DDUTL Disable data micro TLB load
The read/write Memory Region Remap Register overrides the setting specified in the
MMU page tables, and the default behavior if the MMU is disabled.
The Memory Region Register has four fields for remapping instruction-side memory
regions and four fields for remapping data-side memory regions.
You can access the Memory Region Remap Register with the instructions in
Table B-11.
Instruction
MRC p15, 0, Rd, c15, c2, 0
MCR p15, 0, Rd, c15, c2, 0
Figure B-9 shows the bit fields of the Memory Region Remap Register.
SBZ
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Table B-11 Memory Region Remap Register instructions

Operation
Read Memory Region Remap Register
Write Memory Region Remap Register
16 15 14 13 12 11
IWB IWT

Figure B-9 Memory Region Remap Register format

CP15 Test and Debug Registers
Description
0 = Enable I-micro TLB load
1 = Disable I-micro TLB load
0 = Enable D-micro TLB match
1 = Disable D-micro TLB match
0 = Enable D-micro TLB load
1 = Disable D-micro TLB load
0 = Enable I-micro TLB load
1 = Disable I-micro TLB load
10 9 8 7 6 5 4 3
INCB DWB DWT
INCNB DNCB
DNCNB
2 1 0
B-15