Table 3-15 Ipcmperiphid0 Register Bit Assignments; Figure 3-8 Peripheral Identification Register Bit Assignments - ARM PrimeCelL PL320 Technical Reference Manual

Programmer's Model
Actual register bit assignment
Conceptual register bit assignment
3-20
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Configuration
7
31
Configuration

Figure 3-8 Peripheral Identification Register bit assignments

Note
When you design a system memory map then you must remember that the register has
a 4KB-memory footprint. All memory accesses to the peripheral identification registers
must be 32-bit, using the LDR
The Peripheral Identification Registers are described in the following subsections:
• Peripheral Identification Register 0
• Peripheral Identification Register 1 on page 3-21
• Peripheral Identification Register 2 on page 3-21
• Peripheral Identification Register 3 on page 3-21.
Peripheral Identification Register 0
The hard-coded IPCMPeriphID0 Register defines the reset value. Table 3-15 lists the bit
assignments for the IPCMPeriphID0 Register.
Copyright © 2003, 2004. ARM Limited. All rights reserved.
Revision Designer Designer
number 1
0 7 4 3 0 7
24 23 20 19 16 15
Designer
Revision
number
and STR instructions.

Table 3-15 IPCMPeriphID0 Register bit assignments

Bits Name
[31:8] -
[7:0] PartNumber0
Part Part
0 number 1 number 0
4 3 0 7
12 11 8 7
Part number
Description
Read undefined
These bits read back as
ARM DDI 0306B
0
0
0x20