Figure 2-2 Application Program Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

2.3.2 Special-purpose Program Status Registers (xPSR)
ARM DDI 0337B
The r13, r14, and r15 registers have the following special functions:
Stack pointer Register r13 is used as the Stack Pointer (SP). Because the SP
ignores writes to bits [1:0], it is autoaligned to a word, four-byte
boundary.
Handler mode always uses SP_main, but Thread mode can be
configured to use either SP_main or SP_process.
Link register Register r14 is the subroutine Link Register (LR).
The LR receives the return address from PC when a Branch and
Link (BL) or Branch and Link with Exchange (BLX) instruction is
executed.
The LR is also used for exception return.
At all other times, you can treat r14 as a general-purpose register.
Program counter Register r15 is the Program Counter (PC).
Bit 0 is always 0, so instructions are always aligned to word or
halfword boundaries.
Processor status at the system level breaks down into three categories. They can be
accessed as individual registers, a combination of any two from three, or a combination
of all three using the MRS and MSR instructions:
• Application PSR
• Interrupt PSR on page 2-6
• Execution PSR on page 2-7.
Application PSR
The Application PSR (APSR) contains the condition code flags. Before entering an
exception, the Cortex-M3 processor saves the condition code flags on the stack. You can
access the APSR with the MSR(2) and MRS(2) instructions.
Figure 2-2 shows the fields of the APSR.

Figure 2-2 Application Program Status Register bit assignments

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Programmer's Model
2-5