Table 4-2 Cpuid Bit Register Assignments - ARM Cortex-M0 Technical Reference Manual

System Control
4.2.1 CPUID Register
31
Bits Field
[31:24] Implementer
[23:20] Variant
[19:16] Constant
[15:4] Partno
[3:0] Revision
4-4
The CPUID characteristics are:
Purpose Contains the part number, version, and implementation
information that is specific to this processor.
Usage constraints There are no usage constraints.
Attributes See the System control registers on page 4-3.
Figure 4-1 shows the CPUID bit register assignments.
24 23
Implementer Variant
Table 4-2 shows the CPUID register bit assignments.
Function
Implementer code:
= ARM.
0x41
Implementation defined. In ARM implementations this is the major revision number n in the
rn part of the rnpn revision status, Product revision status on page xii:
.
0x0
Indicates the architecture, ARMv6-M:
.
0xC
Indicates part number, Cortex-M0:
.
0xC20
Indicates revision. In ARM implementations this is the minor revision number n in the pn part
of the rnpn revision status, see Product revision status on page xii. For example, for release
r0p0:
.
0x0
Copyright © 2009 ARM Limited. All rights reserved.
20 19 16 15
Constant
Figure 4-1 CPUID bit register assignments

Table 4-2 CPUID bit register assignments

Non-Confidential
4 3
Partno Revision
ARM DDI 0432C
0
ID112415