Figure 8-8 Debug Communications Channel Status Register - ARM ARM966E-S Technical Reference Manual

Debug Support
8-20
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R
The function of each register bit is described here:
Bits 31:28 Contain a fixed pattern that denotes the EmbeddedICE-RT version
number (in this case 0011).
Bits 27:2 Are reserved.
Bit 1 Denotes whether the communications data write register is available
(from the viewpoint of the processor).
If, from the viewpoint of the processor, the communications data write
register is free (W=0), new data can be written.
If the register is not free (W=1), the processor must poll until W=0.
From the viewpoint of the debugger, when W=1, new data is written that
can be scanned out.
Bit 0 Denotes whether there is new data in the communications data read
register.
If, from the viewpoint of the processor, R=1, there is some new data that
can be read using an
From the viewpoint of the debugger, if R=0, the communications data
read register is free, and new data can be placed there through the scan
chain. If R=1, this denotes that data previously placed there through the
scan chain is not collected by the processor, and so the debugger must
wait.
From the viewpoint of the debugger, the registers are accessed using the scan chain in
the usual way. From the viewpoint of the processor, these registers are accessed using
coprocessor register transfer instructions.
You must use the following instructions:
MRC p14, 0, Rd, c0, c0
This returns the debug communications control register into Rd.
MCR p14, 0, Rn, c1, c0
register.
MRC p14, 0, Rd, c1, c0
Copyright © 2000 ARM Limited. All rights reserved.

Figure 8-8 Debug communications channel status register

instruction.
MRC
This writes the value in Rn to the communications data write
This returns the debug data read register into Rd.
ARM DDI 0186A