Table B-9 Cache Debug Control Register Bit Assignments; Figure B-7 Cache Debug Control Register Format - ARM ARM926EJ-S Technical Reference Manual

CP15 Test and Debug Registers
B.1.5 Cache Debug Control Register
31
B-12
The data to be written or read is placed in ARM register Rd with the format shown in
Figure B-4 on page B-8.
The Cache Debug Control Register is used to force specific cache behavior required for
debug.
The following instructions can be used to access the Cache Debug Control Register:
MRC{cond} p15,7,<Rd>,c15,c0,0 ; read cache debug control register
MCR{cond} p15,7,<Rd>,c15,c0,0 ; write cache debug control register
The Cache Debug Control Register format is shown in Figure B-7.
The Cache Debug Control Register bit assignments are listed in Table B-9. The reset
value of the Cache Debug Control Register is
Bit Name Function
[31:3] - Reserved
[2] DWB Disable write-back (force WT)
[1] DIL Disable ICache linefill
[0] DDL Disable DCache linefill
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SBZ

Figure B-7 Cache Debug Control Register format

0x0

Table B-9 Cache Debug Control Register bit assignments

DWB
DIL
DDL
.
Description
Read = Unpredictable
Write = Should Be Zero
0 = Enable write-back behavior
1 = Force write-through behavior
0 = Enable ICache linefills
1 = Disable ICache linefills
0 = Enable DCache linefills
1 = Disable DCache linefills
3 2 1 0
ARM DDI0198D