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Nested Vectored Interrupt Controller
Field
Name
[31:16]
VECTKEY
[31:16]
VECTKEYSTAT
[15]
ENDIANESS
[14:11]
-
[10:8]
PRIGROUP
8-22
Figure 8-10 shows the fields of the Application Interrupt and Reset Control Register.
Figure 8-10 Application Interrupt and Reset Control Register bit assignments
Table 8-16 describes the fields of the Application Interrupt and Reset Control Register.
Table 8-16 Application Interrupt and Reset Control Register bit assignments
Definition
Register key. Writing to this register requires
the write value is ignored.
Reads as
0xFA05
Data endianness bit:
1 = big endian
0 = little endian
ENDIANESS is sampled from the BIGEND input port during reset. ENDIANESS
cannot be changed outside of reset.
Reserved
Interrupt priority grouping field:
PRIGROUP
Split of pre-emption priority from subpriority
0
7.1 indicates seven bits of pre-emption priority, one bit of subpriority
1
6.2 indicates six bits of pre-emption priority, two bits of subpriority
2
5.3 indicates five bits of pre-emption priority, three bits of subpriority
3
4.4 indicates four bits of pre-emption priority, four bits of subpriority
4
3.5 indicates three bits of pre-emption priority, five bits of subpriority
5
2.6 indicates two bits of pre-emption priority, six bits of subpriority
6
1.7 indicates one bit of pre-emption priority, seven bits of subpriority
7
0.8 indicates no pre-emption priority, eight bits of subpriority
Copyright © 2005, 2006 ARM Limited. All rights reserved.
0x5FA
in the VECTKEY field. Otherwise
ARM DDI 0337B
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