Table B-10 Mmu Debug Control Register Bit Assignments; Figure B-8 Mmu Debug Control Register Format - ARM ARM926EJ-S Technical Reference Manual

CP15 Test and Debug Registers
31
B-14
You can access the MMU Debug Control Register using the following instructions:
MRC{cond} p15,7,<Rd>,c15,c1,0 ; read MMU debug control register
MCR{cond} p15,7,<Rd>,c15,c1,0 ; write MMU debug control register
The MMU Debug Control Register format is shown in Figure B-8.
The MMU Debug Control Register bit assignments are given in Table B-10. The reset
value of the MMU Debug Control Register is
Bit Name Function
[31:8] - Reserved
[7] DMTMI Disable main TLB matching for
instruction fetches
[6] DMTMD Disable main TLB matching for data
accesses
[5] DMTLI Disable main TLB load because of
instruction fetch miss
[4] DMTLD Disable main TLB load because of
data access miss
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SBZ

Figure B-8 MMU Debug Control Register format

0x0

Table B-10 MMU Debug Control Register bit assignments

8 7 6 5 4
DMTMI
DMTMD
DMTLI
DMTLD
DIUTM
DDUTM
DIUTL
DDUTL
.
Description
Read = Unpredictable
Write = Should Be Zero
0 = Enable matching
1 = Disable matching
0 = Enable matching
1 = Disable matching
0 = Enable TLB load
1 = Disable TLB load
0 = Enable TLB load
1 = Disable TLB load
3 2 1 0
ARM DDI0198D