B2.35 Disr_El1, Deferred Interrupt Status Register, El1 - ARM Cortex-A76 Core Technical Reference Manual

B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1
The DISR_EL1 records the SError interrupts consumed by an
Bit field descriptions
DISR_EL1 is a 64-bit register, and is part of the registers Reliability, Availability, Serviceability (RAS)
functional group.
63
0
RES
RES0, [63:32]
A, [31]
RES0, [30:25]
IDS, [24]
RES0, [23:13]
AET, [12:10]
EA, [9]
RES0, [8:6]
DFSC, [5:0]
100798_0300_00_en
32
Reserved, .
RES0
Set to 1 when ESB defers an asynchronous SError interrupt. If the implementation does not
include any synchronizable sources of SError interrupt, this bit is
Reserved, .
RES0
Indicates the type of format the deferred SError interrupt uses. The value of this bit is:
Deferred error uses architecturally-defined format.
0
Reserved, .
RES0
Asynchronous Error Type. Describes the state of the core after taking an asynchronous Data
Abort exception. The possible values are:
Uncontainable error (UC).
000
Unrecoverable error (UEU).
001
Note
The recovery software must also examine any implemented fault records to determine the
location and extent of the error.
Reserved, .
RES0
Reserved, .
RES0
Data Fault Status Code. The possible values of this field are:
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B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1

ESB
31 30 25 24 23
A
IDS
Figure B2-31 DISR_EL1 bit assignments, DISR_EL1.IDS is 0
reserved.
Non-Confidential
B2 AArch64 system registers
instruction.
13 12 10 9 8 6
AET
EA
.
RES0
5 0
DFSC
B2-194