Domain Access Control; Table 3-11 Domain Access Control Register, Access Control Bits; Table 3-12 Interpreting Access Permission (Ap) Bits - ARM ARM926EJ-S Technical Reference Manual

Memory Management Unit
3.4

Domain access control

3-24
MMU accesses are primarily controlled through the use of domains. There are 16
domains and each has a two-bit field to define access to it. Two types of user are
supported:
• clients
• managers.
The domains are defined in the domain access control register, CP15 c3. Figure 2-7 on
page 2-18 shows how the 32 bits of the register are allocated to define the 16 two-bit
domains.
Table 3-11 defines how the bits within each domain are interpreted to specify the access
permissions.

Table 3-11 Domain access control register, access control bits

Value Meaning
0 0 No access
0 1 Client
1 0 Reserved
1 1 Manager
Table 3-12 shows how to interpret the Access Permission (AP) bits and how their
interpretation is dependent on the R and S bits (Control Register c1 bits [9:8]).
AP
0 0
0 0
0 0
0 0
Copyright © 2001-2003 ARM Limited. All rights reserved.
Description
Any access generates a domain fault.
Accesses are checked against the access permission bits in
the section or page descriptor.
Reserved. Currently behaves like the no access mode.
Accesses are not checked against the access permission
bits so a permission fault cannot be generated.

Table 3-12 Interpreting access permission (AP) bits

S R Privileged permissions
0 0 No access
1 0 Read-only
0 1 Read-only
1 1 Unpredictable
User permissions
No access
No access
Read-only
Unpredictable
ARM DDI0198D