Table 8-27 Memory Manage Fault Address Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
Bits Field
[2] DWTTRAP
[1] BKPT
[0] HALTED
Bits Field
[31:0] ADDRESS
8-40
Table 8-26 Debug Fault Status Register bit assignments (continued)
Function
Data Watchpoint and Trace (DWT) flag:
1 = DWT match
0 = no DWT match.
The processor stops at the current instruction or at the next instruction.
BKPT flag:
1 = BKPT instruction execution
0 = no BKPT instruction execution.
The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return
PC points to breakpoint containing instruction.
Halt request flag:
1 = halt requested by NVIC, including step. The processor is halted on the next instruction.
0 = no halt request.
Memory Manage Fault Address Register
Use the Memory Manage Fault Address Register to read the address of the location that
caused a Memory Manage Fault.
The register address, access type, and Reset state are:
Address 0xE000ED34
Access Read/write
Reset state Unpredictable
Table 8-27 describes the field of the Memory Manage Fault Address Register.

Table 8-27 Memory Manage Fault Address Register bit assignments

Function
Mem Manage fault address field. ADDRESS is the data address of a faulted load or store
attempt. When an unaligned access faults, the address is the actual address that faulted. Because
an access can be split into multiple parts, each aligned, this address can be any offset in the range
of the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of
the fault. See Memory Manage Fault Status Register on page 8-32.
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