Table 8-26 Bit Functions Of The Memory Manage Fault Address Register; Table 8-27 Bit Functions Of The Bus Fault Address Register - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
Field Name
[31:0] ADDRESS
Field Name
[31:0] ADDRESS
8-38
Table 8-26 describes the field of the Memory Manage Fault Address Register.

Table 8-26 Bit functions of the Memory Manage Fault Address Register

Definition
Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt.
When an unaligned access faults, the address is the actual address which faulted. Because an
access can be split into multiple parts, each aligned, this address can be any offset in the range of
the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of the
fault. See Memory Manage Fault Status Register on page 8-30.
Bus Fault Address Register
Use the Bus Fault Address Register to read the address of the location that generated a
Bus Fault.
The register address, access type, and Reset state are:
Address
0xEEE0ED38
Access Read/write
Reset state Unpredictable
Table 8-27 describes the fields of the Bus Fault Address Register.
Definition
Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an
unaligned access faults, the address is the address requested by the instruction, even if that is not
the address which faulted. Flags in the Bus Fault Status Register indicate the cause of the fault.
See Bus Fault Status Register on page 8-31.
Software Trigger Interrupt Register
Use the Software Trigger Interrupt Register to pend an interrupt to trigger.
The register address, access type, and Reset state are:
Address
0xE000EF00
Access Write-only
Reset state
0x00000000
Figure 8-21 on page 8-39 shows the fields of the Software Trigger Interrupt Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 8-27 Bit functions of the Bus Fault Address Register

ARM DDI 0337B