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Direct Memory Access (DMA)
5.1
About the DMA interface
5.1.1
Single-port RAM DMA solution
5-2
A DMA port is provided on the ARM966E-S. You can connect this port to the D-SRAM
in the ARM966E-S. This allows direct access to the D-SRAM from outside the
ARM966E-S boundary. If this feature is not required the DMA port is tied off in the
RTL and made redundant. You have the option of interfacing the DMA port to a
dual-port RAM or a single-port RAM, providing the ability to choose the solution that
best meets area, performance, and software requirements.
The DMA port enables direct access to the data RAM, bypassing the CPU core. The
ARM966E-S provides the control logic to access the RAM. The implementation of a
DMA controller is application-specific and so any DMA control logic is instantiated
outside of the ARM966E-S macrocell boundary.
Figure 3-1 on page 3-2 shows DMA addresses directly map to the RAM location in the
data RAM 64MB address space. The RAM controller in the ARM966E-S uses bits
[31:26] of the CPU data address to decode Data RAM address space access. Bits
[31:26], however, are not required to be driven by the DMA controller because DMA
access is always to this address space. RAM aliasing occurs for DMA access in the same
way as aliasing occurs for CPU accesses. See Tightly-coupled SRAM address space on
page 3-3 for more information.
Note
The decision to connect to the DMA port, and to a particular type of RAM, is made prior
to synthesis.
DMA accesses to a single-port RAM must be done through the same interface that the
CPU uses to access the RAM. CPU accesses to the RAM must be prevented while DMA
transfers are taking place. This is done by stalling the core for the duration of the DMA
transfer. The DMA controller requests access to the D-RAM by asserting DMAWait.
When the CPU has been stalled on the next instruction boundary, the ARM966E-S
asserts DMAReady to notify to the DMA controller that it now has ownership of the
RAM and can proceed with the transfer.
The single-port RAM DMA solution must be used where the die area of a dual-port
RAM is not acceptable and the performance impact of stalling the core during DMA
transfers is acceptable.
Figure 5-1 on page 5-3 shows how the ARM966E-S DMA port interfaces to a
single-port RAM.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0186A
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