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Field
Name
[7]
MMARVALID
[4]
MSTKERR
[3]
MUNSTKERR
[1]
DACCVIOL
[0]
IACCVIOL
ARM DDI 0337B
Figure 8-16 Memory Manage Fault Register bit assignments
Table 8-21 describes the fields of the Memory Manage Fault Status Register.
Table 8-21 Memory Manage Fault Status Register bit assignments
Definition
Memory Manage Address Register (MMAR) address valid flag:
1 = valid fault address in MMAR. A memory manage fault can be cleared by a later arriving
fault, such as a bus fault.
0 = no valid fault address in MMAR.
If a MemManage fault occurs which is escalated to a Hard fault because of priority, the Hard
Fault handler must clear this bit. This prevents problems on return to a stacked active
MemManage handler whose MMAR value has been overwritten.
Stacking from exception has caused one or more access violations. The SP is still adjusted
and the values in the context area on the stack might be incorrect. The MMAR is not written.
Unstack from exception return has caused one or more access violations. This is chained to
the handler, so that the original return stack is still present. SP is not adjusted from failing
return and new save is not performed. The MMAR is not written.
Data access violation flag. Attempting to load or store at a location that does not permit the
operation sets the DACCVIOL flag. The return PC points to the faulting instruction. This
error loads MMAR with the address of the attempted access.
Instruction access violation flag. Attempting to fetch an instruction from a location that does
not permit execution sets the IACCVIOL flag. This occurs on any access to an XN region,
even when the MPU is disabled or not present. The return PC points to the faulting
instruction. The MMAR is not written.
Bus Fault Status Register
The flags in the Bus Fault Status Register indicate the cause of bus access faults.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Nested Vectored Interrupt Controller
8-31
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