Table 8-22 Memory Manage Fault Status Register Bit Assignments; Figure 8-17 Memory Manage Fault Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Bits Field
[7] MMARVALID
[6:5] -
[4] MSTKERR
[3] MUNSTKERR
ARM DDI 0337G
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Figure 8-17 shows the bit assignments of the Memory Manage Fault Status Register.

Figure 8-17 Memory Manage Fault Status Register bit assignments

Table 8-22 describes the bit assignments of the Memory Manage Fault Status Register.

Table 8-22 Memory Manage Fault Status Register bit assignments

Function
Memory Manage Address Register (MMAR) address valid flag:
1 = valid fault address in MMAR. A later-arriving fault, such as a bus fault, can clear a memory
manage fault.
0 = no valid fault address in MMAR.
If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard
Fault handler must clear this bit. This prevents problems on return to a stacked active
MemManage handler whose MMAR value has been overwritten.
Reserved.
Stacking from exception has caused one or more access violations. The SP is still adjusted and
the values in the context area on the stack might be incorrect. The MMAR is not written.
Unstack from exception return has caused one or more access violations. This is chained to the
handler, so that the original return stack is still present. SP is not adjusted from failing return
and new save is not performed. The MMAR is not written.
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Nested Vectored Interrupt Controller
7 6 5 4 3 2 1 0
MMARVALID
Reserved
MSTKERR
MUNSTKERR
Reserved
DACCVIOL
IACCVIOL
8-33