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17.2
Processor instruction timings
Instruction type
Size
Data operations
16
Branches
16
Load-store Single
16
Load-store
16
Multiple
Exception
16
generating
Data operations
32
with immediate
Data operations
32
with large
immediate
Bit-field
32
operations
Data operations
32
with 3 register
ARM DDI 0337B
Table 17-1 represents the Thumb-2 subset supported in the ARMv7-M architecture. It
provides cycle information including annotations to explain how instruction stream
interactions will affect timing. System effects, such as running code from slower
memory, are also considered.
Cycles count
1
1 (+P
if PC is destination)
1
1+P
2
1
2
(+P
if PC is destination)
2
1
1+N
(+P
if PC loaded)
-
1
1 (+P
if PC is destination)
1
1
1
1 (+P
if PC is destination)
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 17-1 Instruction timings
Description
ADC, ADD, AND, ASR, BIC, CMN, CMP, CPY, EOR,
LSL, LSR, MOV, MUL, MVN, NEG, ORR, ROR, SBC,
SUB, TST, REV, REVH, REVSH, SXTB, SXTH, UXTB,
and UXTH. MUL is one cycle.
B<cond>, B, BL, BX, and BLX. Note, no BLX with
immediate. If branch taken, pipeline reloads (two cycles
are added).
LDR, LDRB, LDRH, LDRSB, LDRSH, STR, STRB, and
STRH, and "T" variants.
LDMIA, POP, PUSH, and STMIA.
BKPT stops in debug if debug enabled, fault if debug
disabled.
SVC faults to SVCall handler (see ARMv7-M architecture
specification for details).
ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S},
CMP, AND{S}, TST, BIC{S}, EOR{S}, TEQ, ORR{S},
MOV{S}, ORN{S}, and MVN{S}.
MOVW, MOVT, ADDW, and SUBW. MOVW and MOVT
have a 16-bit immediate (so can replace literal loads from
memory). ADDW and SUBW have a 12-bit immediate (so
also can replace many from memory literal loads).
BFI, BFC, UBFX, and SBFX. These are bitwise operations
allowing control of position and size in bits. These both
support C/C++ bit fields (in structs) as well as many
compare and some AND/OR assignment expressions.
ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S},
CMP, AND{S}, TST, BIC{S}, EOR{S}, TEQ, ORR{S},
MOV{S}, ORN{S}, and MVN{S}. No PKxxx
instructions.
Instruction Timing
17-3
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