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ARM9TDMI Processor Core Memory Interface
3.7
ARM9TDMI reset behavior
3-12
When nRESET is driven LOW, the currently executing instruction terminates
abnormally. If GCLK is HIGH, InMREQ, ISEQ, DnMREQ, DSEQ and DMORE
will asynchronously change to indicate an internal cycle. If GCLK is LOW, they will
not change until after the GCLK goes HIGH.
When nRESET is driven HIGH, the ARM9TDMI starts requesting memory again once
the signal has been synchronized, and the first memory access will start two cycles later.
The nRESET signal is sampled on the falling edge of GCLK with the first memory
access starting two cycles later. The behavior of the memory interfaces coming out of
reset is shown in Figure 3-4 on page 3-13.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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