Table of Contents
Advertisement
Instruction cycle timings
11.1
Introduction to instruction cycle timings
11-2
The ARM9E-S core within the ARM966E-S implements a pipelined architecture where
several instructions in different pipeline stages overlap. The instruction cycle timing
tables in the ARM9E-S Technical Reference Manual show the number of cycles required
by an instruction, once it has reached the execute stage of the ARM9E-S core pipeline.
The instruction cycle timing numbers quoted in the ARM9E-S Technical Reference
Manual assume that the ARM9E-S is permanently enabled with the CLKEN input tied
HIGH. This implies that both instruction and data memory connected to the ARM9E-S
are able to perform zero wait state responses to all accesses.
In a system such as the ARM966E-S, the CLKEN input to the ARM9E-S core might
be pulled LOW to stall the processor until the memory system is able to respond to the
access. These stall cycles must be taken into account when calculating the ARM966E-S
instruction cycle timings.
Stall cycles are introduced by the ARM966E-S system controller in the following
circumstances:
•
the internal SRAM cannot always be accessed in a single cycle
•
the access requires an AHB transfer
•
the write buffer is full or being drained.
This chapter describes the cycle counts for both normal operation and the above
circumstances.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0186A
Advertisement
Chapters
Table of Contents
