Figure 4-3 Coprocessor Data Operation Sequence - ARM ARM7TDMI Technical Reference Manual

Coprocessor Interface
4.4.6 Coprocessor data operations
MCLK
Fetch stage
Decode stage
Execute stage
nCPI
(from ARM)
CPA (from
coprocessor)
CPB (from
coprocessor)
D[31:0]
4.4.7 Coprocessor load and store operations
4-10
Coprocessor data operations, CDP instructions, perform processing operations on the
data held in the coprocessor register bank. No information is transferred between the
ARM7TDMI processor and the coprocessor as a result of this operation. An example
sequence is shown in Figure 4-3.
ADD SUB
ADD
Instr fetch Instr fetch
(ADD) (SUB)
The coprocessor load and store instructions are used to transfer data between a
coprocessor and memory. They can be used to transfer either a single word of data, or
a number of the coprocessor registers. There is no limit to the number of words of data
that can be transferred by a single LDC or STC instruction, but by convention no more
than 16 words should be transferred in a single instruction. An example sequence is
shown in Figure 4-4 on page 4-11.
Note
If you transfer more than 16 words of data in a single instruction, the worst case
interrupt latency of the ARM7TDMI processor increases.
Copyright © 2001, 2004 ARM Limited. All rights reserved.
CDP TST SUB
SUB CDP TST
ADD SUB CDP
Instr fetch
Instr fetch
(CDP)
(TST)

Figure 4-3 Coprocessor data operation sequence

SUB
TST SUB
Instr fetch
Instr fetch
(SUB)
ARM DDI 0210C