Figure 6-3 Sequential Instruction Fetches, No Ahb Data Access Required; Figure 6-4 Back-To-Back Ldr, No External Instruction Access; Back-To-Back Ldr Or Str Accesses - ARM ARM966E-S Technical Reference Manual

CLK
HTRANS
HADDR
HRDATA
HREADY
CLK
HTRANS
HADDR
HWRITE
HRDATA
HREADY
ARM DDI 0186A
cannot detect a sequential access and use an address incrementer to perform
back-to-back sequential cycles. All instruction fetches are treated as non-sequential
accesses.
Figure 6-3 shows a series of sequential instruction fetches where any data access being
performed by the ARM9E-S is using the tightly-coupled SRAM. Therefore, data
accesses do not interfere with the instruction fetches.
IDLE NONSEQ
IDLE IA-2
ID-1

Figure 6-3 Sequential instruction fetches, no AHB data access required

Back-to-back LDR or STR accesses

Figure 6-4 shows ARM966E-S bus activity when a sequence of LDR instructions is
executed.
NONSEQ
DA-1

Figure 6-4 Back-to-back LDR, no external instruction access

A series of NONSEQ/IDLE transfers is indicated for each access.
Copyright © 2000 ARM Limited. All rights reserved.
IDLE NONSEQ IDLE
IA-3
ID-2
IDLE NONSEQ IDLE
DA-2
DD-1
Bus Interface Unit
NONSEQ IDLE
IA-4
ID-3 ID-4
NONSEQ IDLE
DA-3
DD-2 DD-3
NONSEQ
IA-5
NONSEQ
DA-4
6-9