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Debug Port
12.2.3
DR scan chain and DR registers
12-10
The JTAG Bypass Register (BYPASS)
Purpose
Bypasses the device, by providing a direct path between TDI and TDO.
Length
1 bit.
Operating mode
When the BYPASS instruction is the current instruction in the IR:
•
in the Shift-DR state, data is transferred from TDI to TDO with a
delay of one TCK cycle
•
in the Capture-DR state, a logic 0 is loaded into this register
•
nothing happens at the Update-DR state.
Order
Figure 12-4 shows the operation of the Bypass Register.
This register is mandatory in the IEEE 1149.1 standard.
There are five physical DR registers:
•
the BYPASS and IDCODE Registers, as defined by the IEEE 1149.1 standard
•
the DPACC and APACC Access Registers
•
an ABORT Register, used to abort a transaction.
There is a scan chain associated with each of these registers. As described in IR scan
chain and IR instructions on page 12-7, the value in the IR register determines which of
these scan chains is connected to the TDI and TDO signals.
The JTAG Device ID Code Register (IDCODE)
Purpose
Device identification. The Device ID Code value enables a debugger to
identify the Debug Port to which it is connected. Different Debug Ports
have different Device ID Codes, so that a debugger can make this
distinction.
This is the JTAG-DP implementation of the Identification Code Register,
see The Identification Code Register, IDCODE on page 12-52.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Figure 12-4 JTAG Bypass Register operation
ARM DDI 0337B
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