Table 9-5 Mpu Region Base Address Register Bit Assignments; Figure 9-4 Mpu Region Base Address Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Memory Protection Unit
31
Field Name Definition
[31:N] ADDR Region base address field. The value of N depends on the region size, so that the base address is
aligned according to an even multiple of size. The power of 2 size specified by the SZENABLE field
of the MPU Region Attribute and Size Register defines how many bits of base address are used.
[4] VALID MPU Region Number valid bit:
1 = MPU Region Number Register is overwritten by bits 3:0 (the REGION value).
0 = MPU Region Number Register remains unchanged and is interpreted.
[3:0] REGION MPU region override field.
9-8

Figure 9-4 MPU Region Base Address Register bit assignments

Table 9-5 describes the fields of the MPU Region Base Address Register.

Table 9-5 MPU Region Base Address Register bit assignments

MPU Region Attribute and Size Register
Use the MPU Region Attribute and Size Register to control the MPU access
permissions. The register is made up of two part registers, each of halfword size. These
can be accessed using the individual size, or they can both be simultaneously accessed
using a word operation.
The sub-region disable bits are unpredictable for region sizes of 32 bytes, 64 bytes, and
128 bytes.
The register address, access type, and Reset state are:
Address
0xE000EDA0
Access Read/write
Reset state Unpredictable
Figure 9-5 on page 9-9 shows the fields of the MPU Region Attribute and Size Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ADDR
N 4 3 0
REGION
VALID
ARM DDI 0337B