Summary Of Processor Registers; Table 3-1 Nvic Registers; Table 3-2 Core Debug Registers - ARM Cortex-M3 Technical Reference Manual

System Control
3.1

Summary of processor registers

3.1.1 Nested Vectored Interrupt Controller registers
Name of register
Interrupt Control Type Register
Auxiliary Control Register
SysTick Control and Status Register
SysTick Reload Value Register
SysTick Current Value Register
SysTick Calibration Value Register
Irq 0 to 31 Set Enable Register
.
.
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Irq 224 to 239 Set Enable Register
Irq 0 to 31 Clear Enable Register
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3-2
This section describes the registers that control functionality. It contains the following:
• Nested Vectored Interrupt Controller registers
• Core debug registers on page 3-5
• System debug registers on page 3-6
• Debug interface port registers on page 3-10
• Memory Protection Unit registers on page 3-11
• Trace Port Interface Unit registers on page 3-12
• Embedded Trace Macrocell registers on page 3-13.
Table 3-1 gives a summary of the Nested Vectored Interrupt Controller (NVIC)
registers. For a detailed description of the NVIC registers, see Chapter 8 Nested
Vectored Interrupt Controller.
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Type
Read-only
Read/write
Read/write
Read/write
Read/write clear
Read-only
Read/write
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.
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Read/write
Read/write
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Non-Confidential

Table 3-1 NVIC registers

Address Reset value
a
0xE000E004
0xE000E008 0x0
0xE000E010 0x00000000
Unpredictable
0xE000E014
Unpredictable
0xE000E018
STCALIB
0xE000E01C
0xE000E100 0x00000000
. .
. .
. .
0xE000E11C 0x00000000
0xE000E180 0x00000000
. .
. .
ARM DDI 0337G
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