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ARM PrimeCelL PL320 Technical Reference Manual

Inter-processor communications module
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PrimeCell
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Inter-Processor
Communications Module (PL320)
Revision: r0p0
Technical Reference Manual
Copyright © 2003, 2004. ARM Limited. All rights reserved.
ARM DDI 0306B
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  • Page 1 PrimeCell ® Inter-Processor Communications Module (PL320) Revision: r0p0 Technical Reference Manual Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Downloaded from...
  • Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

  • Page 3: Table Of Contents

    Register summary ..................3-6 Register descriptions ................3-12 Chapter 4 Programmer’s Model for Test Scan testing ....................4-2 Test registers ....................4-3 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Downloaded from Downloaded from Downloaded from...
  • Page 4 Contents Appendix A Signal Descriptions AMBA AHB signals ..................A-2 Non-AMBA signals ..................A-3 Glossary Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Downloaded from Downloaded from Downloaded from Downloaded from...
  • Page 5 IPCMCFGSTAT Register bit assignments .............. 3-19 Table 3-15 IPCMPeriphID0 Register bit assignments ............... 3-20 Table 3-16 IPCMPeriphID1 Register bit assignments ............... 3-21 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Downloaded from...
  • Page 6 AMBA AHB slave signals ..................A-2 Table A-3 IPCM configuration signals ..................A-3 Table A-4 IPCM interrupt signals ....................A-3 Table A-5 Scan test signals ....................... A-3 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 7 Figure 3-4 IPCMxMODE Register bit assignments ..............3-14 Figure 3-5 IPCMxSEND Register bit assignments ..............3-16 Figure 3-6 Mailbox status ......................3-18 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 8 Peripheral Identification Register bit assignments ..........3-20 Figure 3-9 PrimeCell Identification Register bit assignments ........... 3-22 Figure 4-1 IPCMTCR Register bit assignments ................. 4-3 viii Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 9: Preface

    Revision r0p0 PrimeCell Inter-Processor Communications Module (PL320) Technical Reference Manual (TRM). It contains the following sections: • About this manual on page x • Feedback on page xiv. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 10: About This Manual

    Identifies the minor revision or modification status of the product. Intended audience This manual is written for hardware engineers who have some experience of using ARM SoC design flow and methodology. Prior experience of the PrimeCell IPCM is not assumed. Using this manual...
  • Page 11 Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com.

  • Page 12: Key To Timing Diagram Conventions

    Prefix R Denotes AXI read channel signals. Prefix W Denotes AXI write channel signals. Suffix n Denotes AXI, AHB, and APB reset signals. Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 13 8'b1111 is an eight-bit wide binary value of b00001111. Further reading This section lists publications by ARM Limited, and by third parties. ARM Limited periodically provides updates and corrections to its documentation. See for current errata sheets, addenda, and the ARM Limited http://www.arm.com...

  • Page 14: Feedback

    Preface Feedback ARM Limited welcomes feedback on the IPCM and its documentation. Feedback on the IPCM If you have any comments or suggestions about this product, contact your supplier giving: • the product name • a concise explanation of your comments.

  • Page 15: Introduction

    Chapter 1 Introduction This chapter introduces the Inter-Processor Communications Module (IPCM). It contains the following section: • About the IPCM on page 1-2. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 16: About The Ipcm

    1-32-bit Masked Interrupt Status Register (each bit corresponds to each mailbox). • A 32-bit Configuration Status Register • Integration Test Registers for the interrupt outputs • Peripheral and PrimeCell Identification Registers. Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 17 The programmable features, such as source, destination, mode, and mask, enable the configured IPCM to be used by different cores in different ways, depending on the current application. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com.
  • Page 18 Introduction Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from...

  • Page 19: Functional Overview

    • Functional description on page 2-2 • Functional operation on page 2-4 • Examples of messaging on page 2-18. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 20: Functional Description

    The interrupt generation logic block generates the IPCM interrupt outputs from the current status of all the IPCM mailboxes. Figure 2-2 on page 2-3 shows the integration of the IPCM in a multiprocessing system. Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com.

  • Page 21: Figure 2-2 Ipcm Integration In A Multiprocessing System

    Local AHB Shared AHB Figure 2-2 IPCM integration in a multiprocessing system For information on the Core Identification Module (CIM), see the ARM PrimeCell Core Identification Module (PL321) r0p0 Technical Reference Manual. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved.

  • Page 22: Functional Operation

    Figure 2-3 on page 2-5 shows an example system in which the IPCM is integrated so that IPCMINT[0] is connected to the interrupt controller for Core0 and IPCMINT[1] is connected to the interrupt controller for Core1. Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com.
  • Page 23 IPCM. An IPCM configured to have 32 interrupt outputs has 32 corresponding Channel IDs. The Channel ID programs the Mailbox Source, Mailbox Destination, and Mailbox Mask Registers. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com.

  • Page 24: Table 2-1 Channel Id To Interrupt Mapping

    IPCMINT[16] IPCMINT[17] 0x00020000 IPCMINT[18] 0x00040000 IPCMINT[19] 0x00080000 IPCMINT[20] 0x00100000 0x00200000 IPCMINT[21] IPCMINT[22] 0x00400000 0x00800000 IPCMINT[23] Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 25 • Interrupts and status Registers on page 2-10 • Configuration Status Register on page 2-12 • Usage constraints on page 2-16. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 26 ID to the Mask Set location. The interrupt for that mailbox can be masked out by writing the same Channel ID to the Mask Clear location. You can only write to the Mailbox Mask Register locations after the Mailbox Source Register is defined. Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com.
  • Page 27 0 of the Mailbox Send Register. Only when the destination core sets bit 1 of the Mailbox Send Register does the source ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com.
  • Page 28 Interrupt Status Register contains up to 32 bits, each bit referring to a single mailbox. If a core is using a mailbox in polled mode, it can use the Raw Interrupt Status Register to indicate which mailbox requires attention. 2-10 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com.

  • Page 29: Figure 2-4 Mailbox Interrupt Mapping To Ipcm Interrupt Outputs

    Destination Register, and Mailbox Mask Register. For example, in Figure 2-4, the IPCM has 32 interrupt outputs. Mailbox0 generates bit 0 of the IPCMMIS0-31 buses, while Mailbox31 generates bit 31 of the IPCMMIS0-31 buses. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 2-11 Arrow.com. Arrow.com.

  • Page 30: Table 2-2 Configuring Number Of Mailboxes

    Table 2-2 Configuring number of mailboxes Number of MBOXNUM mailboxes 6'b000001 6'b000010 6'b000011 6'b000100 6'b000101 6'b000110 6'b000111 6'b001000 6'b001001 2-12 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 31 6'b010011 6'b010100 6'b010101 6'b010110 6'b010111 6'b011000 6'b011001 6'b011010 6'b011011 6'b011100 6'b011101 6'b011110 6'b011111 6'b100000 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 2-13 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 32: Table 2-3 Configuring Number Of Interrupts

    6'b000110 6'b000111 6'b001000 6'b001001 6'b001010 6'b001011 6'b001100 6'b001101 6'b001110 6'b001111 6'b010000 6'b010001 6'b010010 6'b010011 2-14 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 33 6'b011110 6'b011111 6'b100000 Note Any setting of INTNUM other than the values shown in Table 2-3 on page 2-14 is unsupported. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 2-15 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 34: Table 2-4 Configuring Number Of Data Registers

    Mailbox Data Register can optionally be updated. When Auto Acknowledge is disabled, the destination core must clear its interrupt by clearing bit 0 of the Mailbox Send Register. 2-16 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com.
  • Page 35 The mailbox automatically sets the acknowledge when the final destination core clears its interrupt. Auto Acknowledge disabled The destination core must send the acknowledge. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 2-17 Arrow.com. Arrow.com. Arrow.com.

  • Page 36: Examples Of Messaging

    Core1 DATANUM =1 A HB bus Figure 2-5 Configuration, messaging from Core0 to Core1 Figure 2-6 on page 2-19 shows the messaging sequence. 2-18 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 37: Figure 2-6 Messaging From Core0 To Core1

    Manual Acknowledge interrupt back to Core0. Core0 reads the IPCMRIS0 Register to determine which mailbox caused the interrupt. Again, only Mailbox0 is indicated. Core0 reads the Acknowledge payload data. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 2-19 Arrow.com. Arrow.com. Arrow.com.

  • Page 38: Figure 2-7 Configuration, Back-To-Back Messaging From Core0 To Core1

    DA TA NUM=1 A HB bus Figure 2-7 Configuration, back-to-back messaging from Core0 to Core1 Figure 2-8 on page 2-21 shows the messaging sequence. 2-20 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com.

  • Page 39: Figure 2-8 Back-To-Back Messaging From Core0 To Core1

    Core0 programs the data payload for the next message, DA7A2222 Core0 clears bit 1 and sets bit 0 of the IPCM0SEND Register to send the interrupt to the destination core. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 2-21 Arrow.com. Arrow.com. Arrow.com.

  • Page 40: Figure 2-9 Configuration, Messaging From Core0 To Cores 1, 2, And 3 Using Auto Acknowledge

    A HB bus Figure 2-9 Configuration, messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge Figure 2-10 on page 2-23 shows the messaging sequence. 2-22 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com.

  • Page 41: Figure 2-10 Messaging From Core0 To Cores 1, 2, And 3 Using Auto Acknowledge

    Core1 clears bit 1 in the IPCM0DSTATUS Register. Core3 reads the IPCMRIS3 Register and reads the data payload. Core3 clears bit 3 in the IPCM0DSTATUS Register. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 2-23 Arrow.com. Arrow.com.
  • Page 42 This example assumes that the IPCM has interrupts enabled and is not in integration test mode. Mailboxes 2-3 are inactive and Auto Acknowledge is disabled. Figure 2-11 on page 2-25 shows the configuration. 2-24 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com.

  • Page 43: Figure 2-11 Configuration, Auto Link Messaging From Core0 To Core1 Using Mailbox0 And Mailbox1

    IPCM1SEND[1:0] IPCM1DR0[31:0] 00000000 DA7A1111 IPCMRIS0[3:0] IPCMRIS1[3:0] IPCMINT[3:0] Figure 2-12 Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 2-25 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 44 Core1 clears bit 0 and sets bit 1 in the IPCM1SEND Register to provide the Manual Acknowledge back to Core0. Note This sends the acknowledge interrupt to Core0. 2-26 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com.
  • Page 45 Core0 clears bit 1 in the IPCM0SEND Register. Core0 reads the optional acknowledge data payload in Core1. Core0 clears bit 1 in the IPCM1SEND Register. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 2-27 Arrow.com. Arrow.com.
  • Page 46 Functional Overview 2-28 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 47: Programmer's Model

    It contains the following sections: • About the programmer’s model on page 3-2 • Register summary on page 3-6 • Register descriptions on page 3-12. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 48: About The Programmer's Model

    For example, when INTNUM is set to 1, only the IPCMRIS0 and IPCMMIS0 Registers are available. When INTNUM is set to 32, all IPCMRIS0 to IPCMRIS31 Registers and IPCMMIS0 to IPCMMIS31 registers are available. Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com.
  • Page 49 Setting DATANUM to 1 means the IPCMxDATA0 Registers are available. Setting DATANUM to 7, means all IPCMxDATA0 to IPCMDATA6 Registers are available. Figure 3-1 on page 3-4 shows the IPCM register map. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 50: Figure 3-1 Ipcm Register Map

    0x840 Mailbox0 Reserved for Interrupt7 0x000 0x838 Figure 3-1 IPCM register map Figure 3-2 on page 3-5 shows the register map for Mailbox0. Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 51: Figure 3-2 Mailbox0 Register Map

    Figure 3-3 shows the register map for each Interrupt0. Raw Interrupt Status Registers 0x804 Masked Interrupt Status Registers 0x800 Figure 3-3 Interrupt0 register map ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 52: Register Summary

    0x03C 0x00000000 See Mailbox Data Registers on page 3-17 0x040-0x0 Reserved for Mailbox1 0x080-0x0 Reserved for Mailbox2 0x0C0-0x0 Reserved for Mailbox3 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 53 Reserved for Mailbox14 0x3C0-0x3 Reserved for Mailbox15 0x400-0x4 Reserved for Mailbox16 0x440-0x4 Reserved for Mailbox17 0x480-0x4 Reserved for Mailbox18 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 54 See Masked Interrupt Status Registers on page 3-17 IPCMRIS0 See Raw Interrupt Status Registers on page 3-18 0x804 0x00000000 0x808-0x8 Reserved for Interrupt1 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 55 Reserved for Interrupt12 0x868-0x8 Reserved for Interrupt13 0x870-0x8 Reserved for Interrupt14 0x878-0x8 Reserved for Interrupt15 0x880-0x8 Reserved for Interrupt16 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 56 Reserved for Interrupt29 0x8F0-0x8 Reserved for Interrupt30 0x8F8-0x8 Reserved for Interrupt31 IPCMCFGSTAT See Configuration Status Register on page 3-18 0x900 3-10 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 57 See PrimeCell Identification Register 2 on page 3-23 0xFF8 0x05 IPCMPCellID3 See PrimeCell Identification Register 3 on page 3-23 0xFFC 0xB1 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 3-11 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 58: Register Descriptions

    Table 3-3 lists the register bit assignments. Table 3-3 IPCMxDSET Register bit assignments Name Function [31:0] Destination Set Used to set bits in the IPCMxDSTATUS Registers 3-12 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 59: Table 3-4 Ipcmxdclear Register Bit Assignments

    The read/write IPCMxMODE Registers define how the mailbox is used. The registers can only be written to when the mailbox is assigned, indicated by a bit in the Mailbox Source Register being set. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 3-13 Arrow.com. Arrow.com.

  • Page 60: Table 3-6 Ipcmxmode Register Bit Assignments

    Mailbox Mask Set Registers The write-only IPCMxMSET Registers set bits in the Mailbox Mask Registers. They can only be written to after the Mailbox Source Register is defined. 3-14 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com.

  • Page 61: Table 3-7 Ipcmxmset Register Bit Assignments

    When cleared, the Mailbox Mask Registers disable the interrupts, enabling the cores to use polling rather than interrupts for messaging. The Mailbox Mask Registers are all cleared when the Mailbox Source Register is cleared. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 3-15 Arrow.com. Arrow.com. Arrow.com.

  • Page 62: Table 3-9 Ipcmxmstatus Register Bit Assignments

    The Mailbox Send Registers are cleared when the Mailbox Source Register is cleared. Figure 3-5 shows the register bit assignments. 2 1 0 Undefined Send Figure 3-5 IPCMxSEND Register bit assignments 3-16 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 63: Table 3-10 Ipcmxsend Register Bit Assignments

    Figure 3-6 on page 3-18 shows how Mailbox0 status is presented to Core0 through the use of two status registers, IPCMMIS0 and IPCMRIS0. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 3-17 Arrow.com. Arrow.com. Arrow.com.

  • Page 64: Table 3-12 Ipcmmisx Register Bit Assignments

    The read-only IPCMCFGSTAT Register indicates the hardware configuration options chosen for implementation of the IPCM. Figure 3-7 on page 3-19 shows the register bit assignments. 3-18 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com.

  • Page 65: Table 3-14 Ipcmcfgstat Register Bit Assignments

    PartNumber[11:0] This is used to identify the peripheral. The product code 0x320 used for the IPCM. DesignerID[19:12] This is the identification of the designer. ARM Limited is 0x41 (ASCII A). Revision[23:20] This is the revision number of the peripheral.

  • Page 66: Table 3-15 Ipcmperiphid0 Register Bit Assignments

    Table 3-15 IPCMPeriphID0 Register bit assignments Bits Name Description [31:8] Read undefined [7:0] PartNumber0 These bits read back as 0x20 3-20 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 67: Table 3-16 Ipcmperiphid1 Register Bit Assignments

    Table 3-18 IPCMPeriphID3 Register bit assignments Bits Name Description [31:8] Read undefined [7:0] Configuration These bits read back as 0x00 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 3-21 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 68: Table 3-19 Ipcmpcellid0 Register Bit Assignments

    Table 3-19 IPCMPCellID0 Register bit assignments Bits Name Description [31:8] Read undefined [7:0] IPCMPCellID0 These bits read back as 0x0D 3-22 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 69: Table 3-20 Ipcmpcellid1 Register Bit Assignments

    Table 3-22 IPCMPCellID3 Register bit assignments Bits Name Description [31:8] Read undefined [7:0] IPCMPCellID3 These bits read back as 0xB1 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. 3-23 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 70 Programmer’s Model 3-24 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 71: Programmer's Model For Test

    This chapter describes the additional logic for functional verification and production testing. It contains the following sections: • Scan testing on page 4-2 • Test registers on page 4-3. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 72: Scan Testing

    This is the recommended method of manufacturing test. During scan testing, ensure that the SCANENABLE signal is driven HIGH. For normal use ensure that SCANENABLE is driven LOW. Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com.

  • Page 73: Test Registers

    ITEN=1 in the IPCMTCR Register. Table 4-2 lists the register bit assignments. Table 4-2 IPCMTOR Register bit assignments Name Function [31:0] IntTest IPCMINT[31:0] output ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 74 Programmer’s Model for Test Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 75 This appendix describes the signals that interface with the IPCM. It contains the following sections: • AMBA AHB signals on page A-2 • Non-AMBA signals on page A-3. ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 76: Table A-1 Amba Ahb Common Signals

    Write data bus HWRITE Input Send or receive core AHB Transfer direction signal. When HIGH, this signal indicates a write and, when LOW, a read Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 77: Table A-3 Ipcm Configuration Signals

    SCANINHCLK Input Scan controller Scan data input for HCLK domain SCANOUTHCLK Output Scan controller Scan data output for HCLK domain ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 78: Copyright © 2003, 2004. Arm Limited. All Rights Reserved

    Signal Descriptions Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 79 Glossary This glossary describes some of the terms used in ARM manuals. Where terms can have several meanings, the meaning presented here is intended. Advanced eXtensible Interface (AXI) This is a bus protocol that supports separate address/control and data phases, unaligned...
  • Page 80 Glossary Advanced Microcontroller Bus Architecture (AMBA) AMBA is the ARM open standard for multi-master on-chip buses, capable of running with multiple masters and slaves. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC).
  • Page 81 Unpredictable instructions must not halt or hang the processor, or any part of the system. A 32-bit data item. Word ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Glossary-3 Arrow.com. Arrow.com. Arrow.com.
  • Page 82 Glossary Glossary-4 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 83 HADDR A-2 IPCMPCellD0-3 Registers 3-22 Customization HCLK A-2 IPCMPCellD1 Register 3-23 number of data registers 2-16 HRDATA A-2 IPCMPCellD2 Register 3-23 ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. Index-1 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 84 IPCMxSEND 3-16 using Auto Link 2-24 IPCMxSOURCE 3-12 Revision status x Numerical conventions xiii Scan test signals A-3 Scan testing 4-2 Index-2 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

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