Preface; About This Book - ARM DSTREAM-ST Reference Manual

About this book

DSTREAM-ST System and Interface Design Reference Guide describes the interfaces of the
DSTREAM-ST debug and trace unit, with details about designing Arm architecture-based devices and
PCBs. This document is written for those using DSTREAM-ST or those designing PCBs.
Using this book
This book is organized into the following chapters:
Chapter 1 Debug and trace interface
The Arm debug and trace interface enables powerful software debug and optimization on an Arm
processor-based target system. It is based on the IEEE 1149.1 (JTAG) interface coupled with
various additional signals. This chapter introduces these signals and describes their use within the
interface.
Chapter 2 Target interface connectors
DSTREAM-ST has an Arm JTAG 20 connector, a CoreSight 20 connector, an auxiliary
connector, and a user I/O connector.
Chapter 3 Target board design
When you design a target board to connect to the DSTREAM-ST unit, you must consider the
rules that are discussed in this chapter.
Glossary
The Arm
terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning
differs from the generally accepted meaning.
See the Arm
Typographic conventions
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<and>
100893_0100_06_en
Glossary is a list of terms used in Arm documentation, together with definitions for those
®
Glossary for more information.
®
Introduces special terminology, denotes cross-references, and citations.
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
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instead of the full command or option name.
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
Denotes language keywords when used outside example code.
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
Copyright © 2017–2019 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential

Preface

About this book
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